Simple BLDC controller

[phyllis]

You're right, I(A) is the avalanche current rating. You can see the avalanche energy rating, 3J, just below it.

There's no independent package current limit value for the IXFZ520N075T2, you have to look at the I(D25) rating. This is 465A but ONLY FOR A CASE TEMP OF 25C!!! Since this is impossible for anything other than a single, very short pulse, you have to derate I(D25) as the package heats up.

Check out Figure 6, Drain Current vs. Case Temperature.

I see, but that is just a "rating" right, tells me nothing about whether it is the silicon or the leads or the epoxy that can't stand it. It's still over 100 amp more at 100 deg C than 4368 at 25C. It's got a smidge lower on resistance than 4368 and is a bit larger slug area too. I've emailed to ask them where to get a few. I never destroyed big fets before, so it would be interesting.
By "case" I assume they are referring to slug (metal base), and not epoxy...?

EDIT: It seems like fig 6 is just a derating to keep junction temp below the rated 175C. Nothing to do with the legs apparently. If you use Rds on vs temp graph (ie 2.7mOhm @ 175C), and the jc c/w number (0.25), you can plot the same graph.

[CamLight]

It really doesn't matter what melts, I guess. The FET is toast.

From what I can tell, there's no independent FET leg or bond wire rating.
You'll easily exceed the max. junction temperature rating though before either of those melt unless you're using very short bursts of current and coming close to I(DM) or I(D25). At a constant 300A, you've got over 110W at the start, rising up to over 220W as it heats up. At I(D25), you've got over 500W!

Considering the difficulty in cooling FETs creating that much heat pretty well insures that the junction will probably melt long anything else does.

[rhitee05]

Unless it specifically says otherwise, the data sheet ratings are usually silicon ratings. Sometimes they include a package or a lead limit, sometimes they don't. IRF I know has a number of separate papers written on package limits and so forth which provide a lot of relevant info, IXYS probably has something similar. The ratings are also usually given under certain conditions which may or may not be realistic, so you have to interpret them according to the application conditions. Taking datasheet ratings at face value is rarely useful without some deeper analysis.

[phyllis]

It really doesn't matter what melts, I guess. The FET is toast.

Well, I want to know. Also, it matters if you want to push the FET, you need to know what is the failure point. That is why I asked about the TO legs. If the legs are a problem, pull the heat from them with fat wires close to the epoxy, or clamp them straight to the sink.

From what I can tell, there's no independent FET leg or bond wire rating.
You'll easily exceed the max. junction temperature rating though before either of those melt unless you're using very short bursts of current and coming close to I(DM) or I(D25). At a constant 300A, you've got over 110W at the start, rising up to over 220W as it heats up. At I(D25), you've got over 500W!

Considering the difficulty in cooling FETs creating that much heat pretty well insures that the junction will probably melt long anything else does.

Probably.

[CamLight]

It really doesn't matter what melts, I guess. The FET is toast.

Well, I want to know.

You're going to have to ask the manufacturer about the failure points for that FET then.
Since the wide legs on that FET obviously have to narrow down considerably as the legs approach the junction, that creates a bottleneck for heat buildup. I'm guessing that this bottleneck (whether bond wire or metal soldered to the die) will fail before the legs do.

Also, it matters if you want to push the FET, you need to know what is the failure point. That is why I asked about the TO legs. If the legs are a problem, pull the heat from them with fat wires close to the epoxy, or clamp them straight to the sink.

In my experience, the bond wires fail before the legs do in TO-cased FETs. But, it all depends on how far you exceed the ratings. Go far enough and both can be damaged, with one just beating out the other to failure. PCB layout and the amount of copper (area and copper trace weight) has a HUGE effect on the leg temperature too. This is critical to keeping the legs from becoming unsoldered. But, if they do come unsoldered, you've exceeded the max FET temperature but so much that FET junction failure will come soon anyway, way before the legs melt.

If you want to exceed TO-cased FET current ratings (which will probably also exceed the junction max. temperature rating) then heat-sinking the legs (via lots of PCB copper, soldered on wires, or clamping to metal) will cool both the legs and the bond wires. Cooling the FET case via it's rear plate cools the bond wires too. Heat is being removed from the junction of the FET, which also pulls heat from the bond wires.

FETs also fail quite often from thermal fatigue. This happens when the FET is heated up and cooled off hundreds of times, gradually loosening bonds between the different parts of the FET, leading to increased internal resistance, admittance of moisture, oxidation, and eventual failure. This happens at temperatures and current levels WAY below the max. ratings.

[texaspyro]

I've found that bond wires almost always fail before legs.

[phyllis]

<snip>
Since the wide legs on that FET obviously have to narrow down considerably as the legs approach the junction, that creates a bottleneck for heat buildup. I'm guessing that this bottleneck (whether bond wire or metal soldered to the die) will fail before the legs do.

Probably narrowing down a bit, but aren't these chips quite huge, covering most of the base plate?

In my experience, the bond wires fail before the legs do in TO-cased FETs. thanks But, it all depends on how far you exceed the ratings. Go far enough and both can be damaged, with one just beating out the other to failure. PCB layout and the amount of copper (area and copper trace weight) has a HUGE effect on the leg temperature too. This is critical to keeping the legs from becoming unsoldered. But, if they do come unsoldered, you've exceeded the max FET temperature but so much that FET junction failure will come soon anyway, way before the legs melt.

If you want to exceed TO-cased FET current ratings (which will probably also exceed the junction max. temperature rating) then heat-sinking the legs (via lots of PCB copper, soldered on wires, or clamping to metal) will cool both the legs and the bond wires. Cooling the FET case via it's rear plate cools the bond wires too. Heat is being removed from the junction of the FET, which also pulls heat from the bond wires.

FETs also fail quite often from thermal fatigue. This happens when the FET is heated up and cooled off hundreds of times, gradually loosening bonds between the different parts of the FET, leading to increased internal resistance, admittance of moisture, oxidation, and eventual failure. This happens at temperatures and current levels WAY below the max. ratings.

I'm not thinking about using PCB, but sandwiching a waterblock between two layers of FETs.

[phyllis]

I've found that bond wires almost always fail before legs.

Is there space for more wires?

[CamLight]

<snip>
Since the wide legs on that FET obviously have to narrow down considerably as the legs approach the junction, that creates a bottleneck for heat buildup. I'm guessing that this bottleneck (whether bond wire or metal soldered to the die) will fail before the legs do.

Probably narrowing down a bit, but aren't these chips quite huge, covering most of the base plate?

Perhaps for that package type, but for some DCB FETs the die is still pretty small compared to the very large case so I don't know:
http://www.ixyspower.com/images/technic ... AN0026.pdf
http://www.ixyspower.com/images/technic ... AN0045.pdf
The extra room is used as a heat spreader to lower the junction-to-sink resistance.

The larger the die, the more expensive it is to manufacture and the harder it is to ensure that the current and temperature is evenly distributed across the die. As the on-state resistance of the IXFZ520N075T2 is about 1mOhm or so, the die can't be much larger than other dies that have a similar resistance spec. Using multiple bond wires and a DCB substrate for the die lets them significantly increase the current rating, and decrease the thermal resistance, for an already existing die.

With an I(D25) of 465A, there's obviously a very good connection between the tabs and die. But, with good thermal characteristics a lot of that increase over another package type can be done without having a larger die.

it's certainly worth trying to contact tech support at IXYS and see if they can get you the dimensional data for the die they used. A lot of manufacturers purchase just the FET die and package it themselves so the info should be available.

[CamLight]

I'm not thinking about using PCB, but sandwiching a waterblock between two layers of FETs.

If no PCB, were you going to connect the FET legs via direct soldering of the wire to the legs?
Always risky (can come unsoldered, hard to safely solder them on, etc.), but it can remove more heat than a PCB depending on how long the wires are, their gauge, and what kind of PCB layout you're comparing it to. Looking forward to seeing your setup as you get it up and running!

[phyllis]

Thanks again, those look like the kind of papers I was looking for (but not hard enough). I did find IXYS' chip catalog, they don't list the good chips, but some of the ones they list are relatively large compared to their package. You're saying that small chips have less Rdson - that is counter-intuitive.

If I can get the FZ package, I would place the phase leads (flippers) on top of each other, and a copper plate underneath. Solder the three together, and glue the plate to the copper sink. The +Ve and ground flippers would curl around the side of the sink and meet the other FET pair's flippers (12 fets). The +Ve and ground bus bars would snug underneath those flippers and be glued to the side of the sink.
So as long as there is water in the sink the solder can not melt.
Something like this:

FZ-on-diamond.jpg

(74.64 KiB) Downloaded 6 times

[CamLight]

<snip> You're saying that small chips have less Rdson - that is counter-intuitive.

Didn't say that.
I said that the IXFZ520N075T2 die couldn't be a lot larger (than other 1mOhm dies) since the on-state resistance spec is about the same as other smaller-cased FET dies with low Rds(on) around 1mOhm.

If I can get the FZ package, I would place the phase leads (flippers) on top of each other, and a copper plate underneath. Solder the three together, and glue the plate to the copper sink. The +Ve and ground flippers would curl around the side of the sink and meet the other FET pair's flippers (12 fets). The +Ve and ground bus bars would snug underneath those flippers and be glued to the side of the sink.
So as long as there is water in the sink the solder can not melt.
[/attachment]

Well, the solder can certainly melt if the water doesn't remove enough heat.
Water-cooling can often be good at removing heat from point sources but it takes a lot of good design (and tons of other stuff like piping, fans, maintenance of the system, etc.) to do the job well. You've got a very interesting setup for the FETs, one I've never seen before, and I'm really looking forward to seeing it come together and hear your reports!

[x88x]

Any recent developments on this controller?

[liveforphysics]

I've found that bond wires almost always fail before legs.

Weird.

For me, it seems like if it happens as a slow over current event that gradually heats up I pop the bond wire of the source side, so it bubbles the case up and lets the magic smoke out on the lower right corner of the epoxy block.

If it's a rapid over-current event, it seems to be about a 50-50 mix of the leg popping like a fuse or the die itself exploding and cracking the case.

[texaspyro]

I count die meltdown as bond failures... but then my most common failure is the die turns to a rather nice short circuit with the bond wires/legs still intact. Very seldom do I have a leg fuse.

[nieles]

hi jeremy,

did you have a chance to test the controller ohter than some no-load testing?
could you post some pictures?

i finaly mastered the art of etching a pcb!
so i can finaly build one of these controllers.

if there is interest, i can organise a group buy for the needed parts (europe only probably)
(minus the MC33033 Chip, i can only find the through hole part on ebay)

[x88x]

I've been wondering about this too. This thread was all abuzz a month or so ago, and then suddenly nothing. It didn't get shelved, did it?

[Alan B]

Jeremy has been having an internet issue causing difficulty accessing ES for the past couple of weeks. Hopefully he will be back shortly.

[x88x]

Jeremy has been having an internet issue causing difficulty accessing ES for the past couple of weeks. Hopefully he will be back shortly.

Ah, ok. Thanks for the info.

[J-aprilia-N]

why is it still on this topic

[deVries]

Thanks for all the great comments and the education on Caps. (I've never really understood why there are so many types of Caps).
I've updated the image and Eagle files in the previous post (4 posts back, on Page 22 of this thread). Maybe this is not the kosher way to make updates, but it saves the littering of file versions throughout a thread. I think these are ready to for print. I'll probably get 6 PCBs made. If you want a PCB, send me a PM.

I'll upload a parts list soon.
Mark.

PS. Man, this takes the 'Simple' out of Simple BLDC Controller.

Just bumping this thread in hopes someone will post that they completed one of these BLDC controllers (original or modded) or knows someone that did. Maybe someone has gone on to mod this original design & made some improvements too?

Jeremy is off ES not actively posting for now, since he is involved in building some kind of off-the-grid house or related project.

Does anyone know of anyone that has continued on with this BLDC project whether original or modded???

Please give an update to this thread or point us to a new thread of related interest.

Thanks!!!

[hardym]

Jeremys Simple BLDC design is pretty solid, I think.
I made a few boards and tried to work a few designs for a good brain.
Jeremy was convinced that the MC13033 was a great chip. I tried several PIC implementations for a brain.

I finally realized that microchip make a chip specific for BLDC controller: 18F2431. I've worked up a brain to couple onto Jeremys brawn design, and it works ok, but it need to spend some time with the over-current detection circuitry. This stuff is hard to debug. I have been on a few test drives with the 18F2431 and Jeremy's brawn board.

MauiMart just bought my last PCB for the Simple BLDC Brawn. I'm hoping that he will report some good successes.

MauiMart says that the old files got trashed from the ES system.
So here are all the eagle files, schematic pic, and parts list. The boards fit nicely in to the enclosure you can see in this thread: viewtopic.php?f=2&t=25748

[mauimart]

I finally got around to populating the "brawn" board I received from hardym. My test results along with commentary follow.

I began by connecting my "brain" board (PIC MCLV develpment board stripped of its blown FET's) to the power board. The PIC was running the software from AN1160 (sensorless BLDC commutation using closed PI loop). Since I had not populated the 12V DC/DC converter from hardym's design, I used a separate power supply for that. Upon power up everything worked as expected. I was able to spin two different motors with 24VDC, the stock Turnigy 80/100-130 and another 80/100 that I wound with 9 turns of #14 in wye configuration.

It was now time to build-up the DC/DC and run another no-load test. Unfortunately the DC/DC was not able to provide enough output current for both the power board and the logic board so I powered the logic board separately again using a power supply. Again, both motors spun up nicely under no load.


http://www.youtube.com/watch?v=8TMRn5TOvIA

The next phase was to step up the voltage using a 12s LiPo pack and apply some loading. I used a 30x12 prop attached to the stock Turnigy. At WOT I was seeing 48 battery amps @ 43V (2064W). You can see this run-up in the following video. I measured the temperature of the FET's and the low-side (non PWM) FET's were warmest at about 60C. The PWM duty cycle was only at 62% at WOT and I'm not sure why. I'll have to look at the software more closely. Nonetheless I was encouraged by the performance of the "simple 6-FET controller". The power in of 2kW is right around what I would need from this motor for my next bike - 3kW would be ideal.


http://www.youtube.com/watch?v=Rj0mz2glt7c

Things were progressing nicely and at this point you might guess what is coming...

Phase III was to run my rewound motor with a load (prop) at 18s. I put another 6s pack in series and began to power up to about 72V knowing quite well that the IRFP4368'S are rated at 75V, giving me 3V of overhead. Once again, all systems go. I began to slowly spool up the throttle and reached 29A @ 67V (roughly 2kW battery input power again). I spooled back down and took a look at the PWM scope traces and noted 74% duty cycle at WOT and roughly 2700rpm (commutation frequency of 311Hz divided by 7 pole pairs times 60 seconds - does this sound right?).

Following the scope analysis I decided to do another spool-up run and measure some FET temperatures. At this point I was feeling confident with the power board and I upped the ante by spooling up more briskly than I had with all the previous runs and that's when the magic smoke (and large sparks and flame) let go. Of course the video camera was not running for this...

I'm not sure why it failed but I have a couple of ideas. I should have stayed at least 25% below max Vds for the MOSFETS. Also I think I should not have pushed my luck with the software running in sensorless mode. Perhaps the traces on the board gave way before the FET's exploded? My next planned test prior to the catastrophic event was to install internal hall sensors into the rewound motor and reload the PIC with sensored code. All in all I think this design has promise. I'm a bit discouraged at this point but if I do continue to work on that elusive controller for the large turnigy outrunners I would consider a 12-FET (100Vds) design with the FET's and caps mounted on bus bars instead of a PCB. I would also add shunts or hall effect current sensors to each individual phase and have the uController shut down or throttle back during over-current situations.

Comments? Anyone else messing around with this design?
over

*EDIT*
I added a video of a sweep through of a PWM commutation cycle at full power, measured at the high-side gate. Note the 70% duty cycle.

http://www.youtube.com/watch?v=JxSm6bpQbI8
*EDIT*

[Bikin_Bob]

Hi Mauimart,

As a silent observer I've been eagerly following development of this BLDC and I'm wondering why the thread has slowed to a crawl. In principle a 6 fet design with plenty of safety margin seems like the best way to go! I saw Jeremy post again & hope that you guys continue. As a mechanical guy I lack the background, otherwise I'd be happy to test & breathe the magic smoke if need be!

Best of luck & Thanks again!

[Burtie]

Hi Mauimart,

That looks like some pretty serious brawn board damage there

Sensorless commutation seems to be a bit of a black art to me.

I have destroyed many $$$ worth of sensorless controllers in the past. Some motors they work well with, some they dont, and one loss of sync event can be all it takes to turn your power board to toast !


I hope you are able to continue your valuable work in this field, It is an area where we badly need to progress.

I wonder if a sensor driven brain, because of its relative simplicity, would prove to be a more reliable driver?

Keep up the good work!
Burtie