Arlo's power stage.... New pics and video on page 22 + 24

[Teh Stork]

Sorry to burst your bubble on capacitor location - but it's really not that good.

006_renamed_23110.jpg (129.92 KiB) Viewed 434 times

As I've outlined in this sketch; The green lines are the inductive loop between D-S (pos and gnd). This is priority number 1 - this is rather big as you can see. Also, a square is never good - you should strive to bring the leads together as much as possible. A solution would be to place a small ceramic capacitor right under the heatsink (shave some off the heatsink), this is marked in blue. If you do a PCB, witch I hope, you could mount electrolytics on the underside - and ceramics on the topside.

I'd like to add that high fet source to lower fet drain connection (phase connection point) isn't (countrary to popular belief) critical. Actually - a higher distance here will result in less ringing overshoot, a positive thing (but keep everything in moderation). When i "eliminated" phase node inductance my prototype ringing went into total avalanche mode with vds reaching 3 times input (but still within avalanche limits), and the ringing frequency was outside range of my cheap scope - with my schools expencive scope, the ringing was clear.

What actually is more important is gate driver placement. To sum up: DS decoupling first. Gate driver second. Phase node lastly.

Let me also add that running field oriented controll (or any controll method with some sort of space vector modulation) will cut down your current ripple by 60-70 % over normal six-step commutation, this is more important than optimizing layout. And before going apeshit over FOC; this is on a BLAC engine. A BLDC engine (trapezoidal bemf) with a six-step commutation can be just as efficient and well behaved as a BLAC sine controlled engine.

It's really dissappoiting to lay down countless hours down into optimizing FOC for use on a BLAC motor, then to have the same or better experience with a cheaper BLDC motor. I hate my HS3540 and 12fet for working as nicely as it does. Only optimalization is field weakening, thats as easy to implement on a blac as a bldc motor.

Getting lost in jibberish here, only want to tell you to observe the whole picture - don't overanalyse I've been down that hole.

[Arlo1]

Sorry to burst your bubble on capacitor location - but it's really not that good.

006_renamed_23110.jpg

As I've outlined in this sketch; The green lines are the inductive loop between D-S (pos and gnd). This is priority number 1 - this is rather big as you can see. Also, a square is never good - you should strive to bring the leads together as much as possible. A solution would be to place a small ceramic capacitor right under the heatsink (shave some off the heatsink), this is marked in blue. If you do a PCB, witch I hope, you could mount electrolytics on the underside - and ceramics on the topside.

I'd like to add that high fet source to lower fet drain connection (phase connection point) isn't (countrary to popular belief) critical. Actually - a higher distance here will result in less ringing overshoot, a positive thing (but keep everything in moderation). When i "eliminated" phase node inductance my prototype ringing went into total avalanche mode with vds reaching 3 times input (but still within avalanche limits), and the ringing frequency was outside range of my cheap scope - with my schools expencive scope, the ringing was clear.

What actually is more important is gate driver placement. To sum up: DS decoupling first. Gate driver second. Phase node lastly.

Let me also add that running field oriented controll (or any controll method with some sort of space vector modulation) will cut down your current ripple by 60-70 % over normal six-step commutation, this is more important than optimizing layout. And before going apeshit over FOC; this is on a BLAC engine. A BLDC engine (trapezoidal bemf) with a six-step commutation can be just as efficient and well behaved as a BLAC sine controlled engine.

It's really dissappoiting to lay down countless hours down into optimizing FOC for use on a BLAC motor, then to have the same or better experience with a cheaper BLDC motor. I hate my HS3540 and 12fet for working as nicely as it does. Only optimalization is field weakening, thats as easy to implement on a blac as a bldc motor.

Getting lost in jibberish here, only want to tell you to observe the whole picture - don't overanalyse I've been down that hole.

Ok I am not sure if I understand you?? One peice of angle aluminum is the PHASE and the other is just a heat sync. So the caps will be in the best possible spot as close to the fet body as possible. I just held the cap in place to show an example!

[John in CR]

Why worry about thermally connecting the 2 pieces of angle iron? Does the hi side make more heat than the low side or vice versa? Connecting 2 heat sources together with an expensive material seems like a waste of money to me when it seems all that's needed is a simple insulator. The heat needs to go up to be dissipated away, not sideways toward another source of heat.

I like the modular approach you're doing. This looks simple enough that I could try it. Will we be able to connect our phase wires directly to 3 of the 6 angle iron segments and the battery + to the other 3, or am I missing something about the flow?

John

[Teh Stork]

Ok I am not sure if I understand you?? One peice of angle aluminum is the PHASE and the other is just a heat sync. So the caps will be in the best possible spot as close to the fet body as possible. I just held the cap in place to show an example!

Just meant to stress the point that you need to minimize layout inductance between positive rail and gnd, cap placement is only one piece of the puzzle. The fact that the fets is separated by a heatsink is nice thermally, but not optimal looking at the electical layout.

[Arlo1]

Ok I am not sure if I understand you?? One peice of angle aluminum is the PHASE and the other is just a heat sync. So the caps will be in the best possible spot as close to the fet body as possible. I just held the cap in place to show an example!

Just meant to stress the point that you need to minimize layout inductance between positive rail and gnd, cap placement is only one piece of the puzzle. The fact that the fets is separated by a heatsink is nice thermally, but not optimal looking at the electical layout.

And thats what im getting at. My goal was to get the caps as close to the fet body as possible and be able to place multiple caps for every fet and keep the distance from all fets to all caps as close to the same as possiblle. I showed my layout as an example not as a finished product. But i have a feeling you dont understand how its going to work. I think its as close to perfact as i can get with leaded fets.

[Arlo1]

Why worry about thermally connecting the 2 pieces of angle iron? Does the hi side make more heat than the low side or vice versa? Connecting 2 heat sources together with an expensive material seems like a waste of money to me when it seems all that's needed is a simple insulator. The heat needs to go up to be dissipated away, not sideways toward another source of heat.

I like the modular approach you're doing. This looks simple enough that I could try it. Will we be able to connect our phase wires directly to 3 of the 6 angle iron segments and the battery + to the other 3, or am I missing something about the flow?

John

Aluminum or copper john. Not iron. Aluminum is cheeper and more rigid but i do want the best. One set of fets will run a little hotter because pwm is done on the hi or low side of a controller but not both.
The goal is to have the angle under the fets take the heat away as fast as possible hence the graphite paper! Then the top of the angle can be big and conduct to anysort of heat sink you want. Also the angle under the fets should be thick enough it can absorb heat before getting to hot the thicker the better but the fet legs from drain on the low side to the source on the hi side need to be connected and if they are to long it will cause stray inductance.

[nieles]

if you use aluminium angle, be aware that aluminium oxide (Al2O3) is a electrical insulator (if you leave bare aluminum in contact with air, it will form a oxide layer in a few minutes/hours.

[salty9]

Arlo,

Check http://endless-sphere.com/forums/viewtopic.php?f=2&t=33614&sid=f118e9ce37923b3b7ce2e570468844ae. It was based on a post by LFP. He described the soldering process that while not simple was easy enough that I could do it.

[texaspyro]

if you use aluminium angle, be aware that aluminium oxide (Al2O3) is a electrical insulator (if you leave bare aluminum in contact with air, it will form a oxide layer in a few minutes/hours.

More like under a millisecond...

[Arlo1]

Arlo,

Check http://endless-sphere.com/forums/viewtopic.php?f=2&t=33614. It was based on a post by LFP. He described the soldering process that while not simple was easy enough that I could do it.

Ok so im not here to argue and yes there is ways to de-solder and replece fets but im trying to design something easy to build that works awesome.

[Arlo1]

if you use aluminium angle, be aware that aluminium oxide (Al2O3) is a electrical insulator (if you leave bare aluminum in contact with air, it will form a oxide layer in a few minutes/hours.

More like under a millisecond...

Thanks for the warnings guys i will see whats avalible for copper when i have the big fets in my hands

[Arlo1]

A work in progress. When I get the driver stage the way I want I will post the file!

[Lebowski]

I see that you also got PCB s made for the driver stage, cool

I never had PCBs made before but i must say it works much nicer than that universal PCB type stuff, it is definitely more expensive but so much nicer to work with

I'm working on a killer 6 FET now, got me some cool 4x4mm solid copper bar material to beef up the traces. Never had to use a saw to cut wires to length before

[Arlo1]

Ok so I made some progress.... I used a modified driver stage from zombies and I can not get the boot strap caps to charge! Here is where I am.
The plan is to modify my driver borads to be mounted easily. I added 22ohm gate resistors off the driver board which will be on the board in the future.
I am getting a low side pulse to the ir2113 driver but nothing out... I have 14.xx V on the low side for power and the hi side after the diodes is 1.49 (which needs the low side to pulse to charge) I am running 4.85v to the vdd pin on the other side of the ir2113 and the sd pin is grounded. I will have to look more later Im sitting on a ferry to go see my nose DR for a check up then Look at a 1987cbr250r for another conversion... If I dont get this running soon though I will have to build the cbr with a brushed motor:(

There is a black 275v ac cap across each set of fets RIGHT ON THE LEGS it can not get any closer!

[Njay]

Uouuu!! Now that's a beefy controller
Looks like you're getting there!

[Arlo1]

OK so I found a bad fet driver and one of my wires was not good from my 6 pin header.... Somone want to point me to good single row header connectors withougt crimps?? 3pin 5 pin and 6 pin stuff is in need. I have the 2 row 10 pin clip together ribbon cable header conectors and they are awesome.

SO I am getting my low side fet pulse... BUT my hi side will not charge my bootstrap caps past 1.5v.... WHAT do I do? Here is a snap shot of my v1.0 driver board and Zombies shc file.
BTW I tried lots of settings from 10hz and 10us pulse to 99hz with 99us pulse on the low side to charge the boot strap caps with no luck.

[Lebowski]

Hey dude, nice to see you're making progress Pity you put in the wrong diodes (1N5819) though for the bootstrap supply..

Have a look here at the diode's data sheet:
http://www.vishay.com/docs/88525/88525.pdf

Let's say your battery is 100V and you have 15V for the driver supply (as in your schematic). When the low side
is on all is cool, H_return gets pulled to ground and the diodes conduct to charge the bootstrap caps. When
the high side is on H_return is pulled to 100V by the main power FET. This means there's 115-15 = 100V reverse
voltage accross the bootstrap diodes. The 1N5819's are only rated for 40V reverse....

I would use MBR1100 or STPS2150 schottky diodes for the bootstrap (100V or 150V reverse capable).

What you can try is to shutdown the IR2113 with the SD pin (make this high, keep HIN and LIN low) and connect H_return
to gnd. Then measure the bootstrap voltage at pin VB. In steps increase H_return and see what happens (refresh bootstrap
voltage by connecting H_return to gnd inbetween the steps).

Once you've replace the bootstrap diodes and you still got problems, what may be the case is that you have shootthrough
through Q2 and Q4. Increase R1 to fix this.

[nieles]

few questions related to the power buffer

the fets in the power buffer (Q1-Q8) will only see the voltage difference of 15v right? (no need for 100v fets?)

the ir2113 will only supply the gate charge for the mosfets q1-q8, and not the power mosfets right?

[Lebowski]

few questions related to the power buffer

the fets in the power buffer (Q1-Q8) will only see the voltage difference of 15v right? (no need for 100v fets?)

the ir2113 will only supply the gate charge for the mosfets q1-q8, and not the power mosfets right?

Correct. And you must absolutely make sure you solder Q1-8 in the correct spot because you're
mixing NMOS and PMOS FET's here and you must make sure they're in the correct location.

[Arlo1]

Hey dude, nice to see you're making progress Pity you put in the wrong diodes (1N5819) though for the bootstrap supply..

Have a look here at the diode's data sheet:
http://www.vishay.com/docs/88525/88525.pdf

Let's say your battery is 100V and you have 15V for the driver supply (as in your schematic). When the low side
is on all is cool, H_return gets pulled to ground and the diodes conduct to charge the bootstrap caps. When
the high side is on H_return is pulled to 100V by the main power FET. This means there's 115-15 = 100V reverse
voltage accross the bootstrap diodes. The 1N5819's are only rated for 40V reverse....

I would use MBR1100 or STPS2150 schottky diodes for the bootstrap (100V or 150V reverse capable).

What you can try is to shutdown the IR2113 with the SD pin (make this high, keep HIN and LIN low) and connect H_return
to gnd. Then measure the bootstrap voltage at pin VB. In steps increase H_return and see what happens (refresh bootstrap
voltage by connecting H_return to gnd inbetween the steps).

Once you've replace the bootstrap diodes and you still got problems, what may be the case is that you have shootthrough
through Q2 and Q4. Increase R1 to fix this.

Ok So I have to change the scematic to read what I used lol But the Diodes I used are 200v 1n4003-e3/54. This has nothing to do with the fet drivers, What is happening is the current is flowing through the boot strap caps to the phase wire and the phase wires just become ~12.5 volt! Remember this is a realy low resistance motor!

[Arlo1]

OK I just tried unhooking the motor and the bootstrap caps were 2v so..... Where do I go from here? One diode? A resistor between the bootstrap cap and ground?
R1 is at 470ohms right now btw.

[bearing]

I would try to make the secondary stage of the gate driver with BJT instead of FET technology, then there won't be any cross conduction to discharge the bootstrap caps. Use one pair of NPN/PNP in totempole as close to each gate as possible. Optionally a gate resistor between the NPN emitter and FET base to limit the turn on time without limiting the turn off time. I remember seeing a modern NPN/PNP combo in an SMD package, which was purposely made for gate driving, but I can't find it right now. EDIT: I found them. Make a search for "zxgd" on digikey, or use this link:
http://www.digikey.com/scripts/DkSearch ... words=zxgd

I haven't tried this myself, but if I ever get to making my own controller, this would be my first try on driving the gates.

[Arlo1]

If I cant get this to work I'm going back to isolated supplies! IT WAS FAR SIMPLIER!

[bigmoose]

Arlo, stick with the driver design from the IR data sheet. A few points:

1) You do not want to go with lower voltage FET drivers. The data sheet tells you why. Their RDSon is TOO LOW and results in ringing. IR chose 100 V FETs for a reason, the IRFD110, IRFD9110's.

2) the 1N4003 is for 60 Hz rectification. They are too slow for bootstrap. Get a faster diode for the bootstrap. I use an RGP-15D rated DIODE GPP 1.5A 200V 150NS. There are many that will work here. I bought a 3000 pc spool years ago of the RGP-15D and have been using them up. I like to just use a fast diode, not a schottky because of schottky's leakage.

3) Check your wiring over and over.

4) I can't comment on Lubowski's algorithm on turning on the lower FETs of the H bridge. This is key to charging the upper bootstrap caps. I always have my routine do this to precharge bootstrap caps before we use them in the PWM routine.

Somewhere in the above 4 is your problem.

[Arlo1]

Thanks dave. One thing i should add is lebowskies phase voltage mesurement curcuit has 10k resistors hooked to the phase wires then to a set of diodes from positive and negative. When i get home i will try running 12v to the powerstage it self and see what it looks like.