well that's amazing.
i was googling the OZ890 data sheet and ran across your post.
i have one right here in a BMS i shorted out and was gonna see if i could figure out how it works.
this picture is about all i can do. starting in the middle of the bottom row going clockwise: the two sides of the shunt come together with those 01A resistors and caps to ground and each other,
then all the sense wire inputs from B1N to B10P at the upper left corner,
then there is an open corner pin, likely to gate for shunt transistor 10 underneath, then one leg to the left side of that cap and then the next three legs go to the other side of that big cap
then pin 6 on the top row from the left is B11P, open on top and to shunt gate underneath, then B12P, then to shunt gate on 12 underneath,
then an open pin and then to a leg going back over to R13 on top, which is connected on top of B12P.
then power comes in on pin 12 from above through a 10ohm resistor and diode from the top of the battery. there is a fuse on top of this BMS that attaches to the top of the battery in front of the diode and that goes to a big TVS that has 0837 label with NF underneath
then open, likely to grd underneath, then two ground legs to a through hole that has a ground lead with the diodes for the data connector then a big ground shield goes underneath the chip in the upper right corner and the top right pin is tied to the ground there, then 2 open, then the 2 communications legs, then open, maybe all those are ground shields for the communications link, then another data comm trace
then 7 down from the upper right is a ground shield that runs under the diodes throught that 100 ohm surface mount
pin 8 is attached to the the 1 meg resistor that runs up to the 2k resistor coming off the cathode of that diode attached to the drain of the output FETs. that may be a 'reverse bias to the output' signal to shut down if the output of the BMS is reversed.
then 9 -14 are open, maybe to the ground underneath,
then 15 is attached to the highside of that 1 meg resistor, between it and the cathode is the 2k resistor. so this could be the sink of the reversed biased drain?
then pin 16 is the base of the transistor on the other side for the charging FET gate drive
then the lower right corner on the bottom row is open, ground?
then 2 from the right is source of current to the gate drive transistor for the charging FET, with a diode and cap in parallel to ground
then pin 3 from the right is the gate drive for the output FETs, no intermediate transistor to drive the output FET gate
then ground on 4 then 3 open and then the next is back to one side of the shunt. this is where i started.
i destroyed this one by shorting out the base of the charging FET transistor to ground while it was powered, and the collector too. still haven't figured the transistor labeled VBs for the charging FET gate drive. gonna go power it up now that i looked at it and see if there is some way to bring it back to life.
the voltage on the gate when it was turned on was 10V.
sure wish i had not blown it up.
the chip is limited from what i read because the programming is not open, and the chips are restricted to large orders inside china, and the data sheet is available from wangfang but i don't wanna pay for it. if you get a copy, lemme know.
also i read about how if the R13 lead on the top of cell 12 is left open then the chip will be damaged so that is why they added the extra stuff on top of my 12S BMS setup i bet. so it has a copy of B12 at B13 so the extra traces there on the top row, but no extra trace for the base of the shunt transistor. because shunt 13 doesn't exist.
i think it is designed with lithium ion cells, LIPO, in mind, seemed like the balancing procedure in this setup was more similar to the lipo type balancing but with the setpoints adjusted for lifepo4 in the software.
but they say the processor will handle up to the full 13 cells, so 54.6V at 13S lipo at 4.2V.
