Calculating controller power input capacitance

Njay

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In my long term 350A peak 72V DC brushed motor controller project, I've been playing around with some way of calculating the necessary power input capacitance, at least to have an initial estimate. So I came up with a "method" and would like to ear your opinions on this.

Late note: The scenario assumed is that of a stalled, very low inductance/resistance motor.

I start by setting up 2 main questions:

1) How much capacitance?
2) At what maximum ESR?

For 1) I take the energy stored at the wiring inductance and postulate that the capacitance must be able to store at least the same amount of energy for a defined maximum raise of voltage at the capacitance (that is, at the controller's power input). I decided that a variation of 4V maximum would be acceptable. There's no special reason for this value unless that it is small enough to keep things under control but also big enough to allow some relaxation of requirements. The energy stored in an inductor is EL(i) = 1/2 x L x i^2 and the capacitor one is EC(v) = 1/2 x C x v^2 . The energy the capacitor must absorb from the inductor is what can be contained in a 4V or less variation. Therefore we have EL(350A) <= EC(72V + 4V) - EC(72V) {NOTE: should have used the minimum battery voltage, see posts below}. I assumed the capacitor starts from the battery voltage (Vbat), which I believe to be an acceptable assumption to start with, since although the capacitor is charged 4V above Vbat, it will strongly discharge when the controller turns the power switches ON on the next cycle.
We have all data except the wiring inductance. For that I assumed a worst case scenario of having 2m length of AWG4 wire, and used well-known approximate formulas (checked with other sources), obtaining 2.64uH (and about 1.7mOhm resistance). To play on the safe side, I decided to use 5uH inductance as the value to work with. Now I have all data for the calculation to find out the value of C:

1/2 x 5uH x 350^2 <= 1/2 x C x (72V + 4V)^2 - 1/2 x C x (72V)^2 <=>
C >= 1,035mF

Now for 2), I need to see that once the power switches turn off on the controller at 350A current, the wiring inductance wants to keep pushing 350A somewhere. This somewhere is mainly the capacitance, and its ESR must allow 350A in with a maximum 4V voltage drop. I assumed the capacitor was at Vbat when it starts to be charged by the wiring inductance. So, we have the "ideal" capacitor with Vbat on one side of the ESR and 350A being pushed from the other side of the ESR; applying Ohm's Law,

ESR x 350A <= 4V
ESR <= 11.4mOhm

I then put this through a SPICE simulation using a current source with a sawtooth waveform, rising linearly in 10us to 350A (late note: that's a 2uH winding inductance motor, ouch!), then dropping to 0A in 250ns and repeat within 100us (~10KHz PWM), trying to simulate that there's an inductor (motor) being driven.

controllerinputcapacita.png


I had to either increase the capacitance to 2mF or decrease ESR to 9mOhm for the ripple to be within the target design of 4V maximum (with the calculated values I got 5.5V maximum). I guess this difference should be expected since I calculated both parameters as if they didn't influence one another (ESR slows down charging of capacitor).

After some simulations on SPICE I also concluded that the capacitance should be made much higher because of... resonance. If the switching frequency is low, like in the 5KHz, we start seeing the wiring inductance resonating with the capacitance and the inductor starts "dumping" current back at the battery! So here's another formula, the resonance frequency of a series LC circuit: Fr = 1 / (2 x pi x SQRT(L x C)) . For the values I calculated, the frequency is 2.25KHz. Increasing capacitance to 10mF we lower the resonant frequency to 711Hz, a much safer place when PWMing at 5KHz :).
This is interesting because I know some controllers will do something like 1.5KHz PWM frequency at low speed (reduce power dissipation), so they've probably went through this problem.

Besides this I will still need to consider capacitor ripple current and associated heat dissipation.

So what do you think of this analysis?


Note1: 72V is actually already a conservative value, the maximum Vbat the controller will see in my design is ~66V, I got 72V adding 10% K factor

Note2: SPICE file (generated from LTspice):
Code:
L1 N002 in 5µ
C1 N003 0 1.035m
Vbat N001 0 72 Rser=1m
I1 in 0 PULSE(0 350 250n 10u 250n 0 100u 1000)
Resr in N003 11.4m
R2 N001 N002 1.7m
.tran 0 10m 8m
.backanno
.end
 
I have yet to come across any definitive description of a way to calculate this. I think you're on the right track, with a few corrections I'd make.

Your basic approach to calculating the capacitance is good and the calculations seem valid. You should do this calculation for the nominal battery voltage, though, 66V not 72V. I won't prove it here, but that will increase the required capacitance by a little less than 10%.

I disagree with your number for the wire inductance, however. I know they're very widespread, but that doesn't make formulas which claim to calculate the inductance of a single piece of wire any less wrong. Inductance is a meaningless concept unless you consider a loop of wire. Try this calculator: http://www.cvel.clemson.edu/emc/calculators/Inductance_Calculator/wire2.html You need to consider both the size of the wires and their spacing. A reasonable best-case scenario is for two 4 AWG wires (each 0.2" dia) about 0.4" center-to-center, allowing for insulation. For that case I come up with about 1 uH for a 2 m length.

Using your method, assuming 1 uH and 66 V, I come up with 225 uF.

I would add a second approach. We're assuming that the capacitors will supply all of the current for a short period of time. We can use that assumption along with the fundamental cap equation to estimate the required capacitance. I = C dV/dt. We've already defined I and dV (the allowed voltage ripple), we only need to define dt. This is kind of arbitrary, so let's pick 5 us. That works out to a required capacitance of 438 uF.

I agree with your calculation for maximum ESR, with the caveat you already noticed that if you allow 4 V drop due to the capacitance and 4 V due to ESR you'll end up with more than 4 V.

When you simulate this, you should make the rise time of the current waveform equal to the fall time. Remember that the current freewheels when the FET is off, so the rise time of the current is equal to the turn-on time of the FET. Actually, faster, since the current reaches it's full value in less time than the total switching time. Assuming a rise and fall time of 250 ns seems like a reasonable worst-case.

Also don't forget that you will need smaller, low ESR ceramic decoupling capacitors in addition to the big ones. Their low ESR will ease the requirement on the big caps somewhat. You will have several each of the large and small caps, so the net ESR will be their parallel combination.

Now that we've gone through all that, it's all pretty much worthless unless we somehow account for the inductance in these paths. Inductance is the main factor which determines how effective decoupling caps are, not their value. That's difficult to do accurately, and pretty much impossible unless the board is already laid out so you know the trace paths and can calculate inductance. You could try simulating it, using generous estimates for the inductances. Really, the best thing to do is probably just assume your design needs to substantially beat the numbers you calculated above. You'll want several times the capacitance along with lower ESR. One approach is to include room for many caps in the design, then start your testing by putting in just a few and then add more until you get the results you want. That's wasteful of PCB area, but you could always to a 2nd version after you find out exactly how many you need (keeping the layout otherwise the same!).
 
rhitee05 said:
I have yet to come across any definitive description of a way to calculate this. I think you're on the right track, with a few corrections I'd make.

Your basic approach to calculating the capacitance is good and the calculations seem valid. You should do this calculation for the nominal battery voltage, though, 66V not 72V. I won't prove it here, but that will increase the required capacitance by a little less than 10%.

Njay: Ok, I get it, it's because of the V squared term. Less energy in lower voltage. Good catch :).

I disagree with your number for the wire inductance, however. I know they're very widespread, but that doesn't make formulas which claim to calculate the inductance of a single piece of wire any less wrong. Inductance is a meaningless concept unless you consider a loop of wire. Try this calculator: http://www.cvel.clemson.edu/emc/calculators/Inductance_Calculator/wire2.html You need to consider both the size of the wires and their spacing. A reasonable best-case scenario is for two 4 AWG wires (each 0.2" dia) about 0.4" center-to-center, allowing for insulation. For that case I come up with about 1 uH for a 2 m length.

Using your method, assuming 1 uH and 66 V, I come up with 225 uF.

Njay: Perfectly fine by me :). I think they were talking about self-inductance (there's actually a paper on that from 1908 by "Rosa" which is where the formulas are from; I didn't read the paper, just checked if the formulas matched). Anyways the value I used is still very conservative. I'm aware there are other constructions with different inductance, depending on the way your cables are laid out and if there's a ground plane near etc etc, but I had to set on something.

I would add a second approach. We're assuming that the capacitors will supply all of the current for a short period of time. We can use that assumption along with the fundamental cap equation to estimate the required capacitance. I = C dV/dt. We've already defined I and dV (the allowed voltage ripple), we only need to define dt. This is kind of arbitrary, so let's pick 5 us. That works out to a required capacitance of 438 uF.

Njay: Nevertheless I concluded the capacitance should be much higher than calculated because of resonance, which kind of makes the calculated value irrelevant (by either methods).

I agree with your calculation for maximum ESR, with the caveat you already noticed that if you allow 4 V drop due to the capacitance and 4 V due to ESR you'll end up with more than 4 V.

When you simulate this, you should make the rise time of the current waveform equal to the fall time. Remember that the current freewheels when the FET is off, so the rise time of the current is equal to the turn-on time of the FET. Actually, faster, since the current reaches it's full value in less time than the total switching time. Assuming a rise and fall time of 250 ns seems like a reasonable worst-case.

Njay: I don't get it. When the MOSFET's turn on, the current raise rate will depend on the motor's inductance, that's why I put a slow raise of 10us from 0A to 350A (which actually corresponds to an unrealistically low 2uH (72V = L x 350A / 10us) motor winding inductance. The case I'm simulating is where we're working in discontinuous mode, with the current limiting sub-circuit acting to limit maximum current; maybe you're thinking of continuous mode?.

Also don't forget that you will need smaller, low ESR ceramic decoupling capacitors in addition to the big ones. Their low ESR will ease the requirement on the big caps somewhat. You will have several each of the large and small caps, so the net ESR will be their parallel combination.

Now that we've gone through all that, it's all pretty much worthless unless we somehow account for the inductance in these paths. Inductance is the main factor which determines how effective decoupling caps are, not their value. That's difficult to do accurately, and pretty much impossible unless the board is already laid out so you know the trace paths and can calculate inductance. You could try simulating it, using generous estimates for the inductances. Really, the best thing to do is probably just assume your design needs to substantially beat the numbers you calculated above. You'll want several times the capacitance along with lower ESR. One approach is to include room for many caps in the design, then start your testing by putting in just a few and then add more until you get the results you want. That's wasteful of PCB area, but you could always to a 2nd version after you find out exactly how many you need (keeping the layout otherwise the same!).

Njay: Agree with it all. I just feel I need some ballpark number to start with that makes sense, or some method, instead of trowing out a number at random. And work sub-system by sub-system..
 
Njay said:
Nevertheless I concluded the capacitance should be much higher than calculated because of resonance, which kind of makes the calculated value irrelevant (by either methods).

Yes, I forgot to mention the frequency approach. That's a good 3rd approach, as you definitely want the L-C corner frequency to be well below your PWM frequency.

Njay said:
I don't get it. When the MOSFET's turn on, the current raise rate will depend on the motor's inductance, that's why I put a slow raise of 10us from 0A to 350A (which actually corresponds to an unrealistically low 2uH (72V = L x 350A / 10us) motor winding inductance. The case I'm simulating is where we're working in discontinuous mode, with the current limiting sub-circuit acting to limit maximum current; maybe you're thinking of continuous mode?.

I suppose you could consider discontinuous-mode operation, but that doesn't seem very realistic. Even if a fast current-limiter shuts off the high-side FET, the current will still free-wheel through the motor. Even a very low inductance/resistance motor (take Arlo's Colossus as an example) will have a L/R time constant on the order of 1 ms at the lowest. At 10 kHz (or even 5 kHz) PWM the current will not reach zero so you're still in continuous mode.

It is a little bit of a moot point though. In the ideal model, until some diodes, transistors, etc. are included the rise and fall will behave identically. So the overshoot you see during turn-off is exactly equal to the undershoot you'd see during turn-on.
 
Ahh... I'm learning alot today, thanks :)! Never thought the current could not reach zero, but in fact, even at in an 8uH Colossus if we assumed such low value as 2 mOhm total resistance (internal + frewheeling devices) that would be... at least 12ms (3x L/R) to get below 10%, so it definitely does not go to zero at any PWM frequency we would use. So current rises from zero only when a PWM block starts and falls to zero when a block ends. It is still a situation to account for, it just doesn't happen on every PWM cycle.
 
Thanks for this thread guys.
 
This is a very interesting thread!!

I have some points wich might be nice to look at

As rhitee said:
- Adding L near the Capacitor shoul be nice to see how the layout of the board is essential
- See how small added ceramic capacitor would do their part of the job

I'll try to help you by learning how LTSpice works.
It would be nice that we agree on the way we do the modelisation of the motor (I don't think yours is the same as jdb http://endless-sphere.com/forums/viewtopic.php?f=30&t=22194&start=45 )


- I think we miss a big point here. I read a lot of application notes on Buck converters today and from what I read, the most important value for the input capacitor is the Ripple current. I think that it maybe the key here too.

Have a nice day
 
Your're welcome Arlo :)

Lagoethe said:
As rhitee said:
- Adding L near the Capacitor shoul be nice to see how the layout of the board is essential
- See how small added ceramic capacitor would do their part of the job
Let's focus here on controller input capacitance only, one thing at a time :)

Lagoethe said:
I'll try to help you by learning how LTSpice works.
Thanks :D! You'll find it pretty easy, assuming you know electronic concepts. You can open and simulate pure SPICE files in it, but it won't draw a schematics for you.

Lagoethe said:
It would be nice that we agree on the way we do the modelisation of the motor (I don't think yours is the same as jdb http://endless-sphere.com/forums/viewtopic.php?f=30&t=22194&start=45 )
Very interesting which I'll have to take time to digest. My point of view for now is that modeling the motor as a simple coil as I've done makes the problem at least as "hard" as modeling with a more realistic (and complex) motor. Trying to keep things simple and addressing one at a time.

Lagoethe said:
- I think we miss a big point here. I read a lot of application notes on Buck converters today and from what I read, the most important value for the input capacitor is the Ripple current. I think that it maybe the key here too.
We didn't. I mention that at the end of the 1st post. It's in fact the only missing part that is still preventing me from picking up the capacitors at the store. As soon as time permits I'm going to finish injecting into the first post the knowledge gathered in the discussion and will propose an analytical method to address ripple current needs in choosing the capacitor. It will have to be a "capacitor bank", of course; putting capacitors in parallel not only increases total capacitance and reduces total ESR, but I think also reduces total ESL (assuming we can apply the rules for inductor in parallel, which are the same as for parallel resistors).
 
Ahh, sorry, I had something else on my mind when I wrote that I was modeling the motor as a simple coil. I'm not, I'm just modeling the electric current behavior, excluding special effects. This makes for a cleaner "test signal".

I've also reach the conclusion, actually, the obvious conclusion, that we're dealing with the exact same problem but on different scales. We have the wiring inductance and then place capacitor at the controller's input to deal with the energy lag of that inductance. Then we "walk" another inch or 2 into the MOSFETs, and again there's inductance on this path and we need to add capacitors to deal with the energy lag, but this time, because the inductance is much smaller, the capacitors are smaller; nevertheless, it's the same calculation.
So, in the end we have to deal with the energy stored at the inductances, and that, at the final stage (on the MOSFETs), can also be done with transient suppressors since the energy is much smaller at that point; other techniques can be used, such as snuber filters as jdb used. Even a few tenths of nH with currents in the 2 - 3 hundreds of A are enough to cause quite a voltage raise when we switch the current under 1us. If we have a good control of the inductance on that "last inch" to the MOSFETs, we can probably safely use their avalanche energy to discharge the inductance. Most (all?) MOSFETs are "avalanche rated" and calculations can be done - again, as long as you have a maximum value for the "last inch" inductance.

The only way to really get rid of the spikes is to avoid generating them in the first place, by increasing the dt of the di/dt; but that bears a price as dissipated energy as we all know.
 
A couple of points.

First, the purpose of the smaller ceramic caps is exactly to compensate for the effects of trace inductance between the large caps and the MOSFETs, as well as for the ESR and ESL within the caps themselves. This value will easily be in the 10's of nH range if not greater. It depends on the quality of the layout.

Having an array of caps does exactly what Njay says it will. The total capacitance is N*C, while the ESR is R/N and the ESL is L/N. This makes the "Q" factor for the array much higher than for a single cap alone. For the ceramic caps, ideally you would have a distributed array with some capacitors near each half-bridge.

Selecting capacitors for appropriate ripple current rating is important. However, it's just as hard to figure out what the appropriate ripple current rating is as it is to figure out the required capacitance amount. You could make a worst-case assumption, for example that the capacitors are required to supply the entire phase current during the transient period. That would let you make a fairly simple RMS calculation. For example, assuming 1 us turn-on and -off times and a 50 us period, that would make the required RMS rating 4% of the maximum phase current. I suspect this worst-case assumption will result in significant over-specification, though. It assumes that the caps carry the entire load for the entire switching period (not likely true), and it doesn't allow any way to allocate the ripple current between the ceramic and electrolytic caps. But, to make a more realistic calculation, I think you would need a fairly accurate SPICE model which takes into account all the various parasitic components which would be time-consuming and difficult to do, not to mention highly design-specific (although entirely possible for the knowledgeable and dedicated).

In all cases the layout is highly important. If you have a smart, neat layout which minimizes the parasitic inductances, then both the required capacitance and ripple current will be lower.

All MOSFETs are avalanche-rated. The rating is usually given in terms of energy, for either single or repetitive pulses. Knowing the desired maximum current and the MOSFET rating (use the repetitive rating here), you can use E = 1/2 * L * I^2 to determine the maximum allowable parasitic inductance. You'd probably want to add a safety factor, too. Avalanche damages MOSFETs simply through internal heating, so if you want to be really thorough this would be included in your heating calculations.
 
http://www.ti.com/lit/an/slta055/slta055.pdf

I promise I'll read it soon.
Seems very interesting.

All we need (and we need it all the time) is a valid model to use Buck converters Application Notice (equivalent Irms, Votage,....).
 
I'll try to give some ideas through my recent web surfing


A- Ripple current of Input Capacitor
For a 3 Phases Inverter, Sinusoidal
Vline = sqrt(3/2) x 1/2 x Vbatt
Assuming efficiency and power factor = 1 ( avoid many terms)
Power = sqrt (3) x Vline x Iline
Iline = Power/( sqrt (3) x Vline) = Power/( sqrt (3) x sqrt(3/2) x 1/2 x Vbatt)
Iline = (2/3) x sqrt(2) x Power / Vbatt
Source: http://www.nxp.com/documents/application_note/APPCHP3.pdf p.262

From next source maximum ripple current input
Ilinkac = 0.5033 Iphirms
I think, but it should be confirmed that Iphirms = Iline
Source: http://www.google.fr/url?sa=t&rct=j&q=peak%20current%20ripple%20inverter&source=web&cd=25&ved=0CEkQFjAEOBQ&url=http%3A%2F%2Fwww.engr.uky.edu%2F~radun%2FEE603%2FLectureNotes%2FPWMinverterLosses.doc&ei=B6jMTsLEGMLb4QSp8_Bx&usg=AFQjCNH9NUG7C8nz-pNdrhsK3x_2XWFjWQ


I take my usual example and not yours, (because this is for a 3phase inverter).
Power=1,5kW
Ubatt=48V
Iline = (2/3) x sqrt(2) x Power / Vbatt = 29 A
Ilinkac= 15 A

B- Capacitor technology
In this source http://www.ecicaps.com/pdf/whitepapers/IEMDC_2009_11310_Final_Rev_4.pdf
Though maths might be wrong, it's proven that a film technology capacitor suits more the application.
If try to find the capacitance of my input capacitor in my example:
Idc = P / Vdc = 31.25A
DeltaV= 48x5%=2.4V
Assuming L = 5µH
using your method (which seems perfect to me), negleting minimum batt voltage issue
EL(31A) <=EC(48+2,4)-EC(48)
1/2 x 5 x10^-6 x 31² = 1/2 x C x (50,4²- 48²)
2,4 x 10^-3 = 118.08 C
C = 20µF

using rhitee method
I = CdV/dt
C = I x dt / dV
dV = 2.4V
dt = 5µs
??? about dt: I know this value is arbitrary. But it must come from somewhere . Why not 20s. Is it linked t rise time, or switching frequency in anny manner ???
C = 31.25 x 5µ / 2.4
C = 65 µF

So here is my point:
I need to find a capacitor with a current ripple of 15A and a capacitance of 65 µF
If I check in Aluminium Electrolytic capacitor of digikey:
Ripple current of 15A
=> Capacitor of at least 4700µF. So as it's written in previous source, there may be problem of energy stock,... This capacitor hold too much for its work
=>Capacitor of at least 34$

I tried to find an suitable capacitor in Digikey Film capacitor. I haven't been able to.

So if anyone has any idea of capacitor with huge ripple current value compared to Capacitance, I'll be all hear.

Have a nice day
 
Just 3 quick notes:

1) Check the resonating frequency of your cable inductance with the capacitor (read above) and adjust your cap value so that the resonating frequency is way below your PWM frequency.

2) You can make a bigger ripple current by putting several caps in parallel, which will also reduce ESR and ESL.

3) Ripple provided in datasheets are for sinus waves in certain frequencies. Ripple rating goes up with increased frequency. The "waveform" we have in controllers consists of spaced, high and short peaks of current at the PWM frequency. Would be interesting to calculate a more realistic value for the RMS of these waveforms; I think this may be why controllers seem to get away with "less demanding" cap characteristics.
 
1) Check the resonating frequency of your cable inductance with the capacitor (read above) and adjust your cap value so that the resonating frequency is way below your PWM frequency.
I'll do it

2) You can make a bigger ripple current by putting several caps in parallel, which will also reduce ESR and ESL.
I'll answer below

3) Ripple provided in datasheets are for sinus waves in certain frequencies. Ripple rating goes up with increased frequency. The "waveform" we have in controllers consists of spaced, high and short peaks of current at the PWM frequency. Would be interesting to calculate a more realistic value for the RMS of these waveforms; I think this may be why controllers seem to get away with "less demanding" cap characteristics.
100% agreed with you. But I tried for a whole day to find the RMS ripple current of the input capacitor and I'm unable to make it. We'll have to find a "big head" here because the key factor of the input capacitor is Ripple current.

What I discovered
http://www.cde.com/catalogs/AEappGUIDE.pdf
start at page 14

I discovered that rated ripple current isn't the max ripple current the capacitor can stand. In fact it's way below it.
I made an excel spred sheet which summarize all the maths made.

The saved Capacitor is:
3000h at 105°, 99mOhms, 1500µF , 30x50mm, 200V
I chose my usual example assuming that ripple voltage = Total ripple / nb of capacitor = 15/2= 7.5A

I also assumed that the capacitor reacted to input capacitor ripple current as if it was a sinusoid ( Which is NOT the case).

I also assumed that all studied capacitor reacted as Cornell Dubilier ones.

For all the other point I Followed the application note.

My conclusions through DIGIKEY playing:
-We don't care about rated Ripple current
-The point we care about is ESR. And we care A LOT
- Max rated T° is also important because 85° max T° is not much in a auto heated metallic box.

So the excel doc is attached.
It could be made a little bit better. My idea is to automatise ( does this word exists?) from data base to have a speed choice between different capacitors. If anyone knows how to make it he's my guest.

Have a nice day
 

Attachments

  • CAPACITOR_XLS.xls
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Lagoethe said:
What I discovered
http://www.cde.com/catalogs/AEappGUIDE.pdf
start at page 14
Oh la la, very good reading indeed...

Lagoethe said:
I chose my usual example assuming that ripple voltage = Total ripple / nb of capacitor = 15/2= 7.5A
I suppose you meant "ripple current". What's "nb"?

Lagoethe said:
My conclusions through DIGIKEY playing:
-We don't care about rated Ripple current
-The point we care about is ESR. And we care A LOT
- Max rated T° is also important because 85° max T° is not much in a auto heated metallic box.
Ok, now that's very important information! I'm gonna need time to digest all of this. Excellent work :)!

p.s.: "automate"
 
1-Ripple current
I think brushed motors works exactly like buck converters then I used a source I found
Calculating ripple current for your case:
http://www.edn.com/article/470432-Reducing_buck_converter_input_capacitance_through_multi_phasing_and_clock_synchronization.php
D is duty = > worst case = 0.5
Vin = Vbatt = 72V
Lf = 8µH (colossus)
Fsw = 10KHz
Then peak to peak riplle voltage in inductor (motor side)
Delta_i_L= Vin x D (1-D)/(Lf x Fsw) = 225A
....
I'll follow anyway
Current ripple rms in input capacitor is
ICin= sqrt(D x( (I_in/D)² x (1-D) + (Delta_i_L)²/12 )
= sqrt(0.5 x( (350/0.5)² x 0.5 + 225²/12))
=sqrt ( 0.5 x ( 245000 + 4218)) = sqrt (124609)
= 353A
Well that's much.
I can't believe your input capacitors will experience so much ripple current.

2- answer
I suppose you meant "ripple current". What's "nb"?
yes. Nb is for number
Ripple current = Total ripple / how many capacitor

3- Furthermore
http://www.cde.com/catalog/switch/power/
On this page we can see the available capacitor for your purpose:

Aluminium Electrolytic: Already spoken in previous message. Little reading about electrolytic capacitor's life expectancy
http://www.newark.com/pdfs/techarticles/cornell/multipliers.pdf

Tantalum: not studied right now

Film: http://www.cde.com/catalogs/UNL.pdf . As I wrote in a previous post, this seems to be perfect for our application. I mean few F Max A. 20€. Not cheap but efficient
I'd like to do the same excel analyse as Aluminium electrolytic. Despite a application note, I miss some parameters to do the maths

Ceramic: not studied right now


4-Last thing
I can't find a way to copy the database of digikey except by copy-paste 250 pages .... If someone have an idea. If another supplier give his data another way

Have a nice day
 
Is there a way to mesure ESR?
I have a L/C meter and would I be able to mesure the inducatance paths to do this calculation more acuratly as I build my power stage?
 
Is there a way to mesure ESR?
What do you mean by measuring ESR ?
ESR we talk about is for Input Capacitors. It's provided by supplier. You can make the maths to find it at a specific load.
I don't really understand the use of measuring it in fact.

But if you think of the resistance and inductance of motors and traces of boards. Then it would be very interesting.
I have some tools at home (cheap cheap cheap) and precision is very important here because we are talking about µH and mOhms, so....

Have a nice day
 
Lagoethe said:
Is there a way to mesure ESR?
What do you mean by measuring ESR ?
ESR we talk about is for Input Capacitors. It's provided by supplier. You can make the maths to find it at a specific load.
I don't really understand the use of measuring it in fact.

But if you think of the resistance and inductance of motors and traces of boards. Then it would be very interesting.
I have some tools at home (cheap cheap cheap) and precision is very important here because we are talking about µH and mOhms, so....

Have a nice day
Some manufacturers lie about ESR, and some don't even provide ESR.
it can be measured with a LCR meter (expensive)
 
So it mesures how fast the cap can charge? Would it be possible to set up a test rig with a resistor and a known sorce voltage hooked to a cap and mesure how fast it charges/discharges with a oscilloscope?
 
I apologize but I still don't understand why you want to measure the ESR.

Also
As I wrote before (and discovered by reading the application notes of electrolytic capacitors) ESR varies (is modified) by the applied load. The ESR won't be the same at a switching frequency of 120Hz and 100KHz. The ESR of a capacitor will also be modified but its temperature. The hotter the less ESR. So measure ESR is very difficult.

Some manufacturers lie about ESR,
Maybe. But for your purpose we need specialized Capacitors which are (I believe) made for specific ESR. Then I do'nt really believe that suppliers would lie on their key factor. I could also say, but it seems as a belief, that we are not the usual customers of Low-ESR capacitor, usually they are sold to huge electronic compagnies (B to B) and specificities are true. Anyway, I can't do anything without beliving the supllier, or I'd do nothing (not much in fact).

and some don't even provide ESR.
About that. I was reading PANASONIC EE an ED ( http://industrial.panasonic.com/www-cgi/jvcr21pz.cgi?E+PZ+3+ABA0112+4++WW http://industrial.panasonic.com/www-cgi/jvcr21pz.cgi?E+PZ+3+ABA0035+4++WW ) (i think) series which are made for high ripple current. I you remember, it's exactly what we want to deal with, with your input capacitors. My problem is that they have no ESR provided. So I can't use the previously used one. More over Pansonic application note is... not interesting. The thing is I can't explain why they don't give ESR for a high ripple current application which is deeply linked.

Have a nice day
 
Lagoethe said:
I apologize but I still don't understand why you want to measure the ESR.

Also
As I wrote before (and discovered by reading the application notes of electrolytic capacitors) ESR varies (is modified) by the applied load. The ESR won't be the same at a switching frequency of 120Hz and 100KHz. The ESR of a capacitor will also be modified but its temperature. The hotter the less ESR. So measure ESR is very difficult.

Some manufacturers lie about ESR,
Maybe. But for your purpose we need specialized Capacitors which are (I believe) made for specific ESR. Then I do'nt really believe that suppliers would lie on their key factor. I could also say, but it seems as a belief, that we are not the usual customers of Low-ESR capacitor, usually they are sold to huge electronic compagnies (B to B) and specificities are true. Anyway, I can't do anything without beliving the supllier, or I'd do nothing (not much in fact).

and some don't even provide ESR.
About that. I was reading PANASONIC EE an ED ( http://industrial.panasonic.com/www-cgi/jvcr21pz.cgi?E+PZ+3+ABA0112+4++WW http://industrial.panasonic.com/www-cgi/jvcr21pz.cgi?E+PZ+3+ABA0035+4++WW ) (i think) series which are made for high ripple current. I you remember, it's exactly what we want to deal with, with your input capacitors. My problem is that they have no ESR provided. So I can't use the previously used one. More over Pansonic application note is... not interesting. The thing is I can't explain why they don't give ESR for a high ripple current application which is deeply linked.

Have a nice day
There's a thread around here where texaspyro talks about all the "name brand" lowESR caps he's tested (just about everything on the market) and how bad they lie. Try searching "crap-ass-itor" or "crap-assitor" or "crapassitor" - thats what he calls them. LFP calls it "datasheet coolaid" - "You're drinking datasheet coolaid" he would say. Manufacturers lie about just about everything; I found out just how bad they lie when I started researching mosfets. The lies are probably to a lesser extent with the capacitors since they're not silicon devices.

What you're saying about ESR changing with different loads and temps and such is true, but they can be tested against the test conditions in the datasheet to verify they're up to snuff. I beleive 1000hz, 50ohm load, at room temp is the norm.

All this, but I agree its not super crucial to test the ESR, especially if you have to buy expensive equipment to do so. Just use more capacitors than you calculate that you need.

I haven't done excessive testing of capacitor ESR myself, so I'm not speaking from experience, just trying to bring a potential fly in the vaseline to your attention
 
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