Modular ESC - Schematic/PCB Review wanted

[hightechasshole]

Hello

I've been a silent reader here on-and off for a few years - and have been working on my first ESC project now.

I'm an absolute beginner in regards to power electronics (unless you include blowing shit up with a capacitor bank ) - but i've tried to avoid the common mistakes, design a PCB that has low stray inductances, massively overspec everything and apply as much of what i've read here in topics such as this one: https://endless-sphere.com/forums/viewtopic.php?f=30&t=55641

The design is a modular FOC controller based on the TMC4671 - it's usage is to replace an always blowing up Odrive 3.6 in a "robot" (Max 1m/s, 800kg, 2WD and 2 castor wheels. Should be able to climb some pretty steep hills - while driving with subcentimeter accuracy).

I'd like to ask for some good old roasting of my design, to minimise the needed iterations, as this project is (of course) quite time critical.

The finished product will consist of 1 Logic PCB (TMC4671), plus 1-n power stages arranged in a stack.
Each power stage will be fitted with a few (probably 2-3) capacitor PCBs to provide ultra low ESR decoupling.
I have a 3d-rendering showing how this fits together.

I tried keeping the high current traces (including gates) as short as possible, and the loop areas as small as possible. The capacitor PCBs will add up to 900uF of ceramic decoupling (300 per PCB) of low ESR low stray inductance decoupling (using busbars).

Voltage:
Most of the parts are specced for 100V+, effectively I'm going to use 12s LiFePo4 (43V) for now.

Current:
The MOSFETs have absolute maximum ratings of 380A continuous and 1200A pulse. With 2 parallel power stages I want to effectively use 100A continuous, 200A short-time (<1 min) motor current. I expect the battery current to stay below 25/50A as the motor will turn quite slow most of the time.

For current measurement I'll use 2 L01Z600S05 from Tamura, which will be connected via pin headers.

I attached the most important datasheets + the schematic of the TMC4671-Eval where I stole part of the design.

Thanks for helping me find my mistakes / giving tips for improvement!

 

[mxlemming]

Hi,
Most obvious omission is ceramics on the power stage, they want to be right right next to the FETs.

Electrolytics are not a bad thing, the ESR actually serves a valuable damping function, without it you can find your Vbus rails ringing.

I made an ESC with a very similar layout to yours, see MESC FOC ESC thread. Lots of testing, results posted etc.

4 layer is cheap compared to the hassle 2 layer causes. A solid plane under the FETs does a very nice job of damping parasitic inductances as well as reducing them.

Consider braking resistors and over voltage protection, especially if not using batteries. If the Trinamic FOC driver is anything like the stepper drivers they make, they are quite happy to let the bus voltage float high under braking. Overcurrent is actually a fairly slow death for MOSFETs, since the power dissipated in them is given by I2R losses e.g.(1000A*1000A*0.001ohm = 1kW) whereas an overvoltage causes avalanche and thus a power dissipation of huge numbers of amps (limited by the bus capacitance ESR, say 20mohm for a few electrolytics) at the full bus voltage (120V ish) *a few hundred amps.. a few tens of kW.

Flipping through the datasheet, this Trinamic chip does not appear to have any meaningful protection against faults. Problem with a lot of "conventional" vendors of this technology is that they are used to working with higher voltage/lower power density motors, which typically have far higher inductances and resistances. Faults are far easier to protect against with higher voltage motors since the inductance is proportional to turns squared whereas the BEMF is proportional to turns. Higher inductance means much slower current buildup, and therefore easier to keep PIDs in check, more time to react, power stages typically have much larger headroom margins etc...

If you can space the FETs a bit wider and put screw holes between them, your clamping and therefore heat dissipation will be better.

1ohm gate resistors will give very very sharp switching, 5ohm minimum IMO.

Snubber values determined after making the stage, they need to be tuned to be a critical damping of whatever ringing frequency you get. If you get.

Why the bootstrap diode? It's included in the gate driver no?

Good luck.

 

[hightechasshole]

Most obvious omission is ceramics on the power stage, they want to be right right next to the FETs.

OK, I was under the impression that my ceramics were close enough inductance wise, but I can easily add a few 1uF 1206 on the bottom of the power stage PCB between the two supply planes. I guess that's close enough? Because to place them on the top would require basically starting from scratch, and adding more distance everywhere else --> more inductance.

Electrolytics are not a bad thing, the ESR actually serves a valuable damping function, without it you can find your Vbus rails ringing.

Well that's awkward I thought the lower the ESR the better. So basically we want low ESL but not necessarily the lowest ESR? Is there a source on that? Because everything i've read on ES so far was "low esr all the way" - but then again I guess low ESR for electrolytic is an entirely different story than for ceramic.

I made an ESC with a very similar layout to yours, see MESC FOC ESC thread. Lots of testing, results posted etc.

4 layer is cheap compared to the hassle 2 layer causes. A solid plane under the FETs does a very nice job of damping parasitic inductances as well as reducing them.

Your project was one of the inspirations for this! But I kinda missed the point about the GND planes. I'm not 100% sure I understood it correctly though: going from my design, should I just add 2 inner GND planes? or 1x GND 1x VDD?

Consider braking resistors and over voltage protection, especially if not using batteries. If the Trinamic FOC driver is anything like the stepper drivers they make, they are quite happy to let the bus voltage float high under braking. Overcurrent is actually a fairly slow death for MOSFETs, since the power dissipated in them is given by I2R losses e.g.(1000A*1000A*0.001ohm = 1kW) whereas an overvoltage causes avalanche and thus a power dissipation of huge numbers of amps (limited by the bus capacitance ESR, say 20mohm for a few electrolytics) at the full bus voltage (120V ish) *a few hundred amps.. a few tens of kW.

I will be using batteries, and only 43V for now. I'll make sure to use short and thick battery cables, and I'm not really worried for the battery internal resistance as they're 50Ah LiFePo4 (and later probably 280Ah)

Flipping through the datasheet, this Trinamic chip does not appear to have any meaningful protection against faults. Problem with a lot of "conventional" vendors of this technology is that they are used to working with higher voltage/lower power density motors, which typically have far higher inductances and resistances. Faults are far easier to protect against with higher voltage motors since the inductance is proportional to turns squared whereas the BEMF is proportional to turns. Higher inductance means much slower current buildup, and therefore easier to keep PIDs in check, more time to react, power stages typically have much larger headroom margins etc...

Well, it's an experiment. ODrive keeps on blowing up on me (3.6 that is, will try Pro in the next few days) and has lower safety margins anyways. VESC is not really made for my use case (STEP/DIR positioning), so at this point I'm just throwing stuff at the wall seeing what sticks. I opted against a driver with fault protection (like TMC6100), mainly because when paralleling power stages independent fault handling could cause more harm than good if a false positive were to happen.

If you can space the FETs a bit wider and put screw holes between them, your clamping and therefore heat dissipation will be better.

Good idea, but as water cooling is still an option it's not really possible. But I'm sure the clamping force will be enough as I only have 40mm between the screws.

1ohm gate resistors will give very very sharp switching, 5ohm minimum IMO.

Snubber values determined after making the stage, they need to be tuned to be a critical damping of whatever ringing frequency you get. If you get.

Noted, I think I'll skip assembly by JLC on snubbers & gate resistors, and just buy a set of different R&C's

Why the bootstrap diode? It's included in the gate driver no?

It is (& won't be populated), but someone told me to add it should I decide to use alternative gate drivers that don't have it - as the ones with internal diodes can tend to be a bit sensitive. That's also what the resistor is for. I've also been told to expect to need up to 1uF of bootstrap capacity to ensure a stable supply, so I've decided to just prepare for all eventualities

Thanks a lot for your help!

 

[mxlemming]

Re. Extra ceramics, i would put them on top so you can clamp to the heatsink. If you use VDC and GND inner planes you can probably get away with just putting a few to the side of the FETs.

The thing about needing a small amount of ESR is an observation I've made from running mine without electrolytics. I had much less ceramic capacitance than you, just added a 47uF 2220 ceramic plus the other pile of ceramics. Wasn't pretty. Big overshoot on plug in and lots of noise and bus ringing when running at low power. Not sure what happens if you have as many as you've put...

Take care with the TI gate driver, I don't think it has a standard pinout. Close but not quite. Check the bootstrap and switch node location.

 

[hightechasshole]

Re. Extra ceramics, i would put them on top so you can clamp to the heatsink. If you use VDC and GND inner planes you can probably get away with just putting a few to the side of the FETs.

The thing about needing a small amount of ESR is an observation I've made from running mine without electrolytics. I had much less ceramic capacitance than you, just added a 47uF 2220 ceramic plus the other pile of ceramics. Wasn't pretty. Big overshoot on plug in and lots of noise and bus ringing when running at low power. Not sure what happens if you have as many as you've put...

Take care with the TI gate driver, I don't think it has a standard pinout. Close but not quite. Check the bootstrap and switch node location.

Thanks, I added a VCC and GND plane on the inner layers, ripped out ~220uF of ceramic (leaving 80uF, which I can reduce further if necessary), and added 1980uF electrolytic (9 caps). I hope to get away with only one capacitor PCB like that. I'll also bodge in 10-20 1uF caps on the backside of the main PCB between the supply planes. I wouldn't have gotten them closer to the MOSFETs inductance wise by placing them on the top side, so the only disadvantage should be the cooling, but I have a lot of vias, so that should be acceptable. I ordered the PCBs now, and I'll report back in 1-2 weeks when they arrive

 

[hightechasshole]

Soo. Took a bit longer to get the PCB's and do some tests, here are the results (and new questions):

I ordered 2 controller boards and 5 power stages.

I killed the first power stage by sending ~30V to the drivers (I ran off 12V lab power supply, connecting 12V and VBATT together. Of course breaking current caused enough voltage rise to make driver popcorn)

I then got it running properly with the second board, fixed some horrible ringing by adding a few 1uF ceramic on the bottom side (thanks @mxlemming for telling me, it was really needed). I think the ringing is quite OK already with even just 1uF per FET (without Motor connected that is).
In the end I added 18uF ceramic, with the big capacitors connected using a tiny bit of wire.



This setup (without the heatsink at that point) seemed to work quite comfortably at ~50A for some time (minutes). I then did some ~100A tests (now with heatsinking and 40V battery), while checking for ringing and VCC stability. VCC ripple was a few volts (4VPP at 80A).


Then: hubris.

I set the current limit to 150 Amps (yikes), entered position mode (effectively locking the motor in position), grabbed the torquy bastard with a wrench, and slowly pulled the shaft around. Current rose fast to 150A, stayed there for about half a second, then: click, tiny bit of white smoke, KABOOM, 12cm flame/arc hybrid thingy shooting out the top.




I don't really think that any of the FETs failed / that there was a shoot-through, because the failure didn't really happen anywhere where high currents should flow in that case (right??). So probably the 150A were just too much for the wimpy 1/0.5oz copper (yes I'm aware that I'm an idiot for even trying that), and then thermal runaway. The MOSFETs and drivers did die in the end, but I suspect that the giant short just sent 40V to everything simultaneously.


I set up the third board with 6uF ceramic + the same electrolytics as before. I used only 6uF to see how bad ripple would get, because I was concerned that I won't have enough space in the final PCB revision. Reason being that I might need thermal vias for the MOSFETs - because I didn't realise that TOLL is not actually meant to be cooled from the top, but via the PCB!

Unfortunately the ceramic capacitors detonated at 30 phase amps after a few minutes! So it seems like they got way too much ripple current (or maybe I damaged them while soldering). Weirdly enough they didn't seem to get hot when I checked a few minutes before. But if they fail @5A/cap I'd need way over 20 caps for 100A... Can that be?


TLDR: the thing actually kinda works - but also makes for a great firework. Not quite sure how to proceed with the ceramics - the other problem *should* be solved easily by going for 4x 2oz copper.

 

[mxlemming]

Nice one, getting close to 150A before it blew isn't a bad first effort. Very not bad for trying to feed that much current through 1oz copper. Generally, I found 1oz copper burns at about 5A/mm trace width.

Really weird place for it to burn, I guess there much have been a short there somehow, or you accidentally had the ground returning to the battery/caps via something there.

You can't mount caps like that, it's really mean. They will crack, and they fail short circuit, so they all go pop if you have a big enough power source. You probably don't need as many as in your pic, but they do need you to treat them gently.

Try adding a copper bar above the MOS, other side of the PCB, no need to spend lots of money on heavy PCB copper

It might be in some way because you lost your capacitor bank (see the other PCB is no longer connected since the copper has fused) that caused all sorts of other destruction.

 

[Jrbe]

What do the raw PC boards look like here?


Those inner corners can end up etched further in than expected.
Maybe this trace was a better path than the large but possibly overloaded plane - until the trace was overloaded?
That inner notch can act sort of as a fuse. Seems like it could be the culprit but I'm not sure why.

 

[hightechasshole]

Generally, I found 1oz copper burns at about 5A/mm trace width.

Ouch.

Really weird place for it to burn, I guess there much have been a short there somehow, or you accidentally had the ground returning to the battery/caps via something there.

That's what I also don't understand. The ground trace (the one Jrbe mentioned) is still intact. I know it doesn't look like it, but that's only burned solder mask, probably due to the heat right next to it. I think the firs thing that went was probably either the outermost via or the connection point between via and inner layer.
Which would mean the current circulating between high side MOSFET 2 and 3 was the cause.

You can't mount caps like that, it's really mean. They will crack, and they fail short circuit, so they all go pop if you have a big enough power source. You probably don't need as many as in your pic, but they do need you to treat them gently.

I did some further tests, carefully soldering only 3x 1uF onto a new board. Tested it up to 60 amps with basically no change in high frequency overshoots. The caps got a bit warm then (visible as a ~2° delta on thermal camera before the MOSFETs heat the entire board). So I think 9 of them should be enough.

It might be in some way because you lost your capacitor bank (see the other PCB is no longer connected since the copper has fused) that caused all sorts of other destruction.

Can't be that, as I fed power not through the XT60 that is on the picture, but through another one connected to the capacitor PCB. The fire stopped when the trace fused (I wasn't fast/ballsy enough to pull the battery connector)

Try adding a copper bar above the MOS, other side of the PCB, no need to spend lots of money on heavy PCB copper

I'll do a redesign because of the thermals anyways.


I have a decision to make there though:

Should I go with something like this: https://www.lcsc.com/product-detail/Multilayer-Ceramic-Capacitors-MLCC-SMD-SMT_TDK-CKG57NX7S2A226MT009W_C342273.html
Where I could place 3 of them to give me 6.6 - 66uF depending on which exact part I choose, but my loop area will be quite a bit bigger

Or should I take normal 1206 (or even 0805) which will not have the strain relief, only 9uF (that's what fits in my new design), but a quite a bit smaller loop area. They would be mounted properly (individual pads with resist around, reflow soldered)

I'm currently leaning towards 0805, as the fast ringing seems to be:
- horrible without ceramics
- acceptable with 3x 1uF
- only a tiny bit better with 20x 1uF

So I'd put my eggs in the "reduce area further" basket.

 

[Botvink]

Very interesting burn...

This made me question the boards I made past.. Meanwhile I ordered a similarly simple 0.5 oz PCB that I'll have it next week, I was thinking that board can drive 50A, but according to this calculation, 15-20A will pass, max...

As for the subject, I haven't seen any MOV or TVS in your design, I recommend putting them in between VDS lines and also motor outputs. It is more effective for ripples than just caps.

As a capacitor, 1210 type 63V-100V series may be more suitable.

 

[hightechasshole]

Just a quick update on this: I completely re-did the layout, brutally optimizing for making all high current loops as tiny as possible & putting lots of ceramic capacitance as close to the FETs as possible. The trade-off is that wiring is kind of a pain in the ass.
I also went for 6 layers 2oz copper this time.


It's surely a very weird looking build, but I think the scope traces speak for themselves (measured @2GSa, with a very thin twisted pair, right at the phase output to ground):




And @28A:




So far I tested to 80a which it handles well, even without cooling for short bursts. My motor doesn't however, so 150-200a tests will have to wait.

Dead-time is probably still ~50-80ns too high, but not gonna frock with that now as it just has to work, and it's gonna get water cooling anyways