Mosfet switching time vs gate measured examples

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zombiess

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Tonight I was playing around with a new gate driver I made testing it out which is based on the TD350E chip with a 15A boost stage. I decided to take some random FET samples and see how long it took to fully saturate them with regards to Vgs and 2 different value gate resistors. It has the 2 level turn off feature enabled which lasts for about 600nS and then I have a 3.9 ohm turn off resistor. To get 6.66 ohms I put a 10 ohm and 20 ohm resistor in parallel. I did not bother measuring the drain to source resistance or putting any D-S voltage. This to measure switching time from 0-Vgs only.

I tuned the gate resistors so that there was not any overshoot in the turn on.

IRFB4110 Qg 150nC
10 ohm = 500nS
6.6 ohm = 333nS

IRFB4115 Qg 77nC
10 ohm = 300nS
6.6 ohm = 250nS

IRFP4568 Qg 151nC
10 ohm = 650nS
6.6 ohm = 400nS

IXFK230N207 Qg 1350nC
10 ohm = 1350nS
6.6 ohm = 950nS
 
If you want high efficiency from the mosfets at high frequencies then you should use minimal gate resistance.
Yes, the EMI level will increase but efficiency goes upp.
Try connecting the gate directly to the gate driver with zero ohm gate resistor and re-measure.

Please note that any high speed connections must have a short patch with a solid ground plane for proper decoupling.
The driver IC shall have a SMD capacitor connected across its power pins. E'g 47uF 16V 1210 X7R is a good value.
Using that solution the problems with overshoot spikes in minimised.
 
Honk, you are missing the point of my post. It's just a simple illustration of how the gate resistor effects the Vgs on time.

It's not OK to go 0 ohm either, I did that and it produces a 5V Vgs overshoot at turn on. I have not tried lower than 6.67ohms yet, but I don't need to as this was only done for the sake of basic data collection on different MOSFETs.

IF we start talking D-S switch times in the above mentioned tests I would be surprised if any of them switched slower than 125nS under load. I did not bother measuring it, but I did see the miller plateau in every MOSFET on the scope traces except for the big IXYS which I had to parallel with a 2nd one to get it to show up at all which was interesting.
 
Honk said:
If you want high efficiency from the mosfets at high frequencies then you should use minimal gate resistance.
Click to expand...


I once also believed that. I thought Bigmoose was crazy telling me to add more gate resistance.

However, adding gate R stopped the resonance bounces I was getting causing my FET to make about 20 oscillations through the trans-conductance area, and the circuit stability and efficiency and reliability and heating all drastically improved by just adding more gate R.

It is silly to make a statement like, "use minimal resistance for optimal performance".

You properly observed and tuned-for-the-circuit gate R and you will have optimal efficiency/performance etc.
 
Futterama said:
Does input capacitance have an influence on the gate rise-fall times?
Click to expand...

Do you mean Ceff or an external gate to source cap? The Ceff can be estimated for a given MOSFET, but I didn't bother to calculate it. The Qg is always specified on data sheets and usually in nano Coulomb's which is what I posted. I did 3 of each type of MOSFET, then averaged and rounded the results to the numbers I posted. It's not scientific, but I did it to see how much the gate charge effects the Vgs on /off time so I could get a better feeling for sizing a gate resistor. With 6.67 ohms the driver with 15v - the ~1v drop of the boost stage is capable of delivering 14v/6.67 = 2.10 peak amps. The gate driver itself only draws 20mA from the power 24v buss so I only have a 1W dc-dc installed.

The above numbers were done with a single bare MOSFET, nothing else connected, just twisted pair gate and source connections with the scope probe on the legs. Twisted vs untwisted made a very noticeable difference in the scope traces.
 
My question for you Zombiess my friend, do you believe it has any meaning to show the switching performance of the FET unloaded?
 
liveforphysics said:
Honk said:
If you want high efficiency from the mosfets at high frequencies then you should use minimal gate resistance.
Click to expand...


I once also believed that. I thought Bigmoose was crazy telling me to add more gate resistance.

However, adding gate R stopped the resonance bounces I was getting causing my FET to make about 20 oscillations through the trans-conductance area, and the circuit stability and efficiency and reliability and heating all drastically improved by just adding more gate R.

It is silly to make a statement like, "use minimal resistance for optimal performance".

You properly observed and tuned-for-the-circuit gate R and you will have optimal efficiency/performance etc.
Click to expand...

HighHopes told me a similar story. Choose the largest value gate resistor that allows for a reasonable switching time with minimal heating. Its a balancing act to minimize ringing, overshot and switch time. My measurements are narrow in scope on purpose because I wanted to compare different MOSFETs. I just thought it would be nice to share the data I collected since I have not seen many talk about this topic. Most people on here only focus on rdson and there is way more to a MOSFET than its conduction losses.

One thing i have not checked yet is how low in resistance I could go before getting overshoot on turn on, I only did the 2 resistor values + 0 ohms shorting the resistor, but those numbers are not a good comparison due to how I shorted the on resistor with an external tool.
 
I would ask the same question as Liveforphysics, with an unloaded coil, you have no parasitic capacitance/inductance that is a major factor in the resonance (ringing). It seems that this is well documented in some of the literature. There is also the issue of sequencing of the bridge elements so that a drain is always on before a source is turned on. With a sine drive, three bridge elements are always active (except at the zero crossing) and that requires that the two crossover bridge drives are setup for make-before-break to keep the current flow continuity. So many questions and it seems so few real answers. Much of the literature does not deal with these questions either.
kenkad
 
liveforphysics said:
My question for you Zombiess my friend, do you believe it has any meaning to show the switching performance of the FET unloaded?
Click to expand...

Absolutely! At least in my case its useful, but to each their own. I personally found this interesting and very little discussion about it on here so I decided to share.

It gives me an idea of how much gate driver I need for a given number of parallel MOSFETs to switch the in a certain amount of time. If I paralleled 4 MOSFETs and saw a good drain to source switch time but then when scoping gate to source switch time I notice its taking 10uS to fully saturate and my Vgs pulses are blurring together due to the time I then know the gas switch time needs to be faster or I need to alter my pwm freq or my dead time. This also shows how much of an effect the gate resistor has on the gas switch time. Yes it will vary some from this under load but this provides a good idea of where to start. Just running the math to estimate the on time is just that, an estimated and that was one of the things I was checking. There is no solid formula I have found that will give accurate real world on times. Needs to be done on the bench. The difference in the on curves with the same current was very eye opening to me, mainly on the ixys MOSFET. It behaved differently than I thought.

Take a look at the ixys MOSFET I have in that list. Would you want parallel MOSFET 2 of them and use a 1.5 amp peak gate driver that had all the features you want? Nope, at least not without a decent boost stage on it.

I should have saved the screen shots of the numbers above as they reveal a lot more information. Trying to measure under load can cause a lot of noise so having a clean reference to look at is good. Not to mention you can then compare it to the same device under loaded conditions.
 
Well, I have designed lots of efficient power stages during my career as power designer. It's my daytime occupation. 8)
I actually suggested using minimal gate resistance, meaning as low as possible without oscillation problems. Often 1-2ohm is fine.
The zero ohms suggestion was only for a comparison test. In some applications the zero ohm works fine at elevated EMI (ok as long as it can pass EMI tests).
If large problems with oscillations occurs, then an optimal SMD design with short signal path and a good solid ground plane is not being used.
At less good driver layouts larger gate resistors is the cure at the expense of higher switching losses. This is a fact, not fiction. :wink:
Btw, gate driver measurements should be tested in a real setup at the intended load of the device for proper results.
 
my take on gate resistors:


Choose the turn-off resistance:
- as low as possible
- but not so low that the gate circuit oscillates (twisting the gate drive wires helps with this respect as a low L allows for a lower R before oscillation occurs)
- and not so low that the resulting current spike blows up the gate drive IC

important for the turn-on resistance is the reverse recovery current of the other FETs diode. When you want to turn the FET on the voltage on it's
gate rises. The FET starts conducting but the drain voltage does not drop yet due to the reverse recovery of the diode of the other FET. The miller
effect does not come into play yet so the gate voltage keeps rising with a slope determined by the gate resistor and the FETs input capacitance.
Together with the transconductance of the FET the current rises with a certain amount of A / usec: for instance if the gate voltage rises with 1V / usec
and the transconductance is 200A/V, the current rises with 200A/usec. Knowing the rate of rise of the current, from the datasheet you can find
how big the reverse recovery current spike will be.
Once the reverse recovery effect stops the drain voltage drops and the miller effect comes into play: now the slope on the output signal is dependent
on the gate drive overvoltage, the gate resistor and the miller capacitor.

So, when chosing the turn-on resistance:
- must be quite high to limit the reverse recovery current spike
- but not too high as this lowers the slope and increases switching losses.

regarding the reverse recovery current: when the reverse recovery stops the power line inductor carries a current equal to the motor phase current
plus the reverse recovery current: the power of this combined current is dumped into the FET that is off (and can blow up this FET when the resulting
temperature spike is too large). Note that the amount of energy dumped in the FET also depends on the power supply voltage as a high supply makes
the power dump last longer !!! We're talking kW's over 100's of n-secs.





P.S. in my young days when I didn't know any better I didn't use any gate resistors (gate resistors ? bull !) This is how I build the controller for my v1 motor,
so far it has done 8000km without any problems, all parts original. What helps is I used 150V parts but only an 80V battery, and only 11A_rms phase current.
 
@Lebowski

Good take on the gate resistors.
You are right, the turn on should be limited by the properly selected gate resistor (varies by design) but the turn off can be fast.

Another view on gate resistors....using a small size e'g SMD 0402 or 0603 together with a tranzildiode it will protect the electronics
from overvoltage if the mosfets breaks down. Any voltage conducting backwards from the gate through the gate resistor is clamped
by the tranzildiode. If the gate spike is large enough then the SMD resistor fuses and the electronics is saved from destruction.
Shall be connected like this: "Mosfet gate -> Resistor - > Tranzildiode between gatedriver output to GND"
 
And regarding a 'clamp' on the gate when the transistor is off:

- the turn-off gate resistor needs a certain value as mentioned before, to prevent ringing
- however, this value may be too high to properly keep the FET off during switching events at its drain.
- only then you need a clamp, but make sure the clamp is activated after the FET has been turned off (with the turn-off gate resistors).
 
If you refer to the tranzildiode clamp mentioned then you have missunderstood me.
A tranzildiode clamp is only there as protection. The clamp voltage should always be set
above maximum gate voltage. E'g at 15V gate voltage the proper tranzil level would be 17V.

It's never being active at normal operation...it will only clamp gate spikes coming from a defective mosfet.
It has saved me countless of times in prototype designs. A mosfet and gate resistor is an easy repair but
large areas of fried SMD electronics is difficult and time consuming to fix.
 
Zomb, "how long it took to fully saturate them with regards to Vgs and 2 different value gate resistors" not nitpicking, but how did you define "fully saturate?" Your times seem a bit longer than I would have expected for the gate resistor chosen and the strength of the driver.
 
bigmoose said:
Zomb, "how long it took to fully saturate them with regards to Vgs and 2 different value gate resistors" not nitpicking, but how did you define "fully saturate?" Your times seem a bit longer than I would have expected for the gate resistor chosen and the strength of the driver.
Click to expand...

That's not nit picking, it's a valid question because as you realize there is some subjectiveness to this. I chose 0V as my start point of course, moved the cursor right to where it started to rise on a 200nS scale. For full saturation I picked a point past the upper knee point where it looked like the gate voltage leveled off. This point is usually between 13-14V depending on the gate resistor/MOSFET.

I think I need to take some scope screen shots with the cursors on the screen so it can be seen exactly how I did it.

I have not mentioned until now that while playing around I was using long 10" twisted leads because I was also experimenting with the amount of twists per inch effecting the scope trace so there is some resistance in the wires which I have not measured. I tried different lengths and twists. Yes the leads are longer than would be used in real life, but I was trying to purposely magnify any effect they had and get a feel for how everything is related to each other. This is something that can only be done on the bench. Playing around with all of this for just one hour was VERY informative for me.

I didn't post this information to start any kind of debate or suggestions on design, just some results that I found were interesting. We have more people getting involved in gate driver and power stage design on here and I have not seen much discussion on this topic. An expert might consider this data totally meaningless, but to someone just starting out it's pretty eye opening, especially when driving a large MOSFET such as the IXYS monster. Things don't always behave how you think they might.
 
That likely explains most of it! You are going well into "saturation" and I am going to 6x% of "saturation."

As for turns per inch, FWIW, I like 1 to 1.6 turns per inch. I chuck mine in a cordless drill and twist. If it is too tight, I stretch it out by running my fingers down the twist to untwist it a bit. Cat 5 pairs are a nice twist and 15pF per foot. Little fragile though in a vibration environment.
 
bigmoose said:
That likely explains most of it! You are going well into "saturation" and I am going to 6x% of "saturation."

As for turns per inch, FWIW, I like 1 to 1.6 turns per inch. I chuck mine in a cordless drill and twist. If it is too tight, I stretch it out by running my fingers down the twist to untwist it a bit. Cat 5 pairs are a nice twist and 15pF per foot. Little fragile though in a vibration environment.
Click to expand...

Yes, I'm driving it with 15V so I'm past the typical 10V Qg chart which only goes to 10 volts in most data sheets. HighHopes gave me the math I'm using for calculating the on time uses Ceff and a 1.4 C rate which represents around 20%-80% of the drive voltage delta. Most of the MOSFETs I am using 150-200v, have a miller plateau in the 6-6.5V range. The IRFB4110 MOSFETs are around 4.0-4.5V if I remember correctly so going to 15V puts me way into saturation. On the next batch if DC-DC converters I buy I'll probably go to 12V versions since I really only need around 10V for solid saturation unless going to 15V buys me something extra advantage I'm not aware of.

The math I'm using to estimate the 20-80% on time (it's not exact, just a ball park number..usually)

effective gate capacitance
Ceff = Qg/delta_Vdr

Time to charge mosfet gate
tpON = 1.4*Rg_ON*Ceff
 
Honk said:
If you refer to the tranzildiode clamp mentioned then you have missunderstood me.
A tranzildiode clamp is only there as protection. The clamp voltage should always be set
above maximum gate voltage. E'g at 15V gate voltage the proper tranzil level would be 17V.

It's never being active at normal operation...it will only clamp gate spikes coming from a defective mosfet.
It has saved me countless of times in prototype designs. A mosfet and gate resistor is an easy repair but
large areas of fried SMD electronics is difficult and time consuming to fix.
Click to expand...
No, :D i'm talking about the extra active clamp that is sometimes added like for instance Arlo does...
 
Lebowski said:
No, :D i'm talking about the extra active clamp that is sometimes added like for instance Arlo does...
Click to expand...

Yup the Miller clamp, the drivers I have only engage it below 2V at turn off and then keep it off until the next pulse releases it.
 
Regarding twisting the gate wires.
zombiess said:
I didn't post this information to start any kind of debate or suggestions on design, just some results that I found were interesting.
Click to expand...
I for one would really like to see your results. I have also been tinkering with the idea to use magnet wire as gate wires since these have a thinner isolation and this would give a closer twist, reducing inductance.
Multi strain 24 AWG silicone wire would also be nice due to flexibility, but I don't think they would hold the twist as good as a stiffer material like magnet wire or normal plastic coated wire.
 
Futterama said:
Multi strain 24 AWG silicone wire would also be nice due to flexibility, but I don't think they would hold the twist as good as a stiffer material like magnet wire or normal plastic coated wire.
Click to expand...

after you solder everything solid the twist has nowhere to go...
 
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