New 16-cell Battery Management System (BMS)
- Thread starter GGoodrum
- Start date
miro13car
100 kW
Any chance 16-circuit BMS will be available, when , what price.
Enthiusiasm seems to go away, Bob, are you there?
MC
Enthiusiasm seems to go away, Bob, are you there?
MC
The LiFePO4 batteries are the answer to the world's prayers.
Bob and Gary's CMS/BMS is the solution to the final technical problems. It promises to protect the battery investment and support faster charging! Thus far unrealized, but fundamental capabilities.
I suspect the suggestions of limited interest are vastly mistaken.
Richard
Bob and Gary's CMS/BMS is the solution to the final technical problems. It promises to protect the battery investment and support faster charging! Thus far unrealized, but fundamental capabilities.
I suspect the suggestions of limited interest are vastly mistaken.
Richard
lawsonuw
1 kW
Any chance of a kit for this BMS showing up? Even just bare PCBs would be helpful. Whatever happens though, a shunt-regulator/LVC BMS like this one will be my first choice when I invest in Lithium. Even if it costs more, this style BMS is worth it because the BMS would rather die than let the attached cells go out of spec. 
Marty
P.S. the end of charge current limiting on this is brilliant. (seems an obvious thing to do now... )
Marty
P.S. the end of charge current limiting on this is brilliant. (seems an obvious thing to do now...
)
GGoodrum
1 MW
I talked to Bob yesterday. His internet connection is via satellite, and he's been having problems with it for over a week now. Very intermittant service, from what he says. In any case, he has been busy with getting caught up with controller mods, and as soon as he is, he will refocus on trying to get some BMS/CMS boards out. I think he is also willing to do kits, or even partial kits. He said he would post something here soon, once he got his connection problems sorted out, and when he had time.
That's all I know.
-- Gary
That's all I know.
-- Gary
PJD
100 W
We probably need to look for a few people to be regional suppliers for the BMS's. Just the boards and a parts list would go a long way.
I'm a bit late to looking at this thread and I certainly haven't read it all, but I took a look brief look at the BMS schematic and there are a number of problems, some of them fairly serious.
In no particular order-
1) You are using 100uf and 1000uf caps on your 4538 one shot circuits, you need a protection diode to Vdd so the caps don't destroy the input protection diodes when the +6V supply collapses. In your case with such high resistances a resistor in series with the timing cap would suffice, something to limit currents to less than 10ma.
2) the above is moot anyway, What were you thinking trying to get 16 minute to 2.5 hours of delay out of an RC?!! Your timing resistor is 10 MEG, we are talking pullup currents in the 100 nanoamp range, the Leakage currents on the capacitors can be 20 Times larger than that! It's very likely that these circuits may never cycle at all. You have to ask yourself 'Do I feel lucky?'
3) Not sure why you bothered with D5 for a reference when you could just have divided the D1 reference down, especially since it makes stability over temperature considerably worse. A minor issue anyway.
4)The input offset voltage of LM358 can be up to +-7mV. With your current circuit design and worse case offset voltage the minimum current limit could be 1.4 amps even with the pot adjusted all the way to 0 volts. Change your design or get a better op-amp.
5) You are limiting gate voltages on Q2-Q3 with a 6.2V zener? This is uncomfortably close to the max Vgs threshold of the FETS especially under cold temperatures, if you get a large current spike you could put the FETs into the linear region and they'll vaporize forthwith. A Vgs in the 10-15V range will also reduce Rdson, possibly by as much as a factor of 2 and reduce your power dissipation in those FETs.
6) However you are also uncomfortably close to exceeding the Vbe reverse breakdown voltage of Q6, so you'll need to put a diode in series with the base of Q6 or the higher Vgs will breakdown the Vbe junction and pull the gate of Q4 up rendering your current limit control inoperative.
7) Using optocouplers for a single supply referenced circuit seems a waste. overly complex, expensive and board space hungry. There are cheaper, simpler, and lower current ways to do this. But that's just parts and expense.
8 But the following really is a killer for me.
I have a real problem with the LVC design. The TC54 trips at 2.1V and pulls the optocoupler diode low flowing about 1 mA initially. You have maybe 200mv drop across the TC54 output at 1ma, maybe 1.2V across the LED and 700mv across the 820 ohm resistor. Initially this is ok. But you've just put a 1ma load on a fully depleted cell! along with the 0.5ma gate drive load of R4 it's going to continue to discharge the battery, how long will it last? At some point the cell voltage will fall low enough that insufficient current will flow through the LED and the gates of Q2-Q3 will turn on again reconnecting the load and fully discharge the cell to 0V damaging it. So at what point will this happen? In a 16 Cell battery lets assume the other cells are at 3v, that's 48V on the the pullup R4 to the gates of Q2-Q3. The opto has to pull that 100k to ground, so it needs to flow almost 500uA. If you have a worst case current transfer ratio of the optoisolator of 100% you'll need to flow 500uA into that optocoupler to keep the gates from turning on. The drop across the LED is maybe 1.2V, the drop across the TC54 output is maybe 0.1V, but as the cell voltage drops this starts to go up fairly rapidly since the gate voltage inside the TC54 is also dropping, say it gets to 0.2V. We need 0.4V across our 820 resistor to keep things working, but that means that somewhere in the range of 1.8V of cell voltage the LVC system stops working and the FETs turn on and discharge the cell to 0V and destroy it. If somebody runs a pack down to cutoff and doesn't recharge it soon.....
ouch
In no particular order-
1) You are using 100uf and 1000uf caps on your 4538 one shot circuits, you need a protection diode to Vdd so the caps don't destroy the input protection diodes when the +6V supply collapses. In your case with such high resistances a resistor in series with the timing cap would suffice, something to limit currents to less than 10ma.
2) the above is moot anyway, What were you thinking trying to get 16 minute to 2.5 hours of delay out of an RC?!! Your timing resistor is 10 MEG, we are talking pullup currents in the 100 nanoamp range, the Leakage currents on the capacitors can be 20 Times larger than that! It's very likely that these circuits may never cycle at all. You have to ask yourself 'Do I feel lucky?'
3) Not sure why you bothered with D5 for a reference when you could just have divided the D1 reference down, especially since it makes stability over temperature considerably worse. A minor issue anyway.
4)The input offset voltage of LM358 can be up to +-7mV. With your current circuit design and worse case offset voltage the minimum current limit could be 1.4 amps even with the pot adjusted all the way to 0 volts. Change your design or get a better op-amp.
5) You are limiting gate voltages on Q2-Q3 with a 6.2V zener? This is uncomfortably close to the max Vgs threshold of the FETS especially under cold temperatures, if you get a large current spike you could put the FETs into the linear region and they'll vaporize forthwith. A Vgs in the 10-15V range will also reduce Rdson, possibly by as much as a factor of 2 and reduce your power dissipation in those FETs.
6) However you are also uncomfortably close to exceeding the Vbe reverse breakdown voltage of Q6, so you'll need to put a diode in series with the base of Q6 or the higher Vgs will breakdown the Vbe junction and pull the gate of Q4 up rendering your current limit control inoperative.
7) Using optocouplers for a single supply referenced circuit seems a waste. overly complex, expensive and board space hungry. There are cheaper, simpler, and lower current ways to do this. But that's just parts and expense.
8 But the following really is a killer for me.
I have a real problem with the LVC design. The TC54 trips at 2.1V and pulls the optocoupler diode low flowing about 1 mA initially. You have maybe 200mv drop across the TC54 output at 1ma, maybe 1.2V across the LED and 700mv across the 820 ohm resistor. Initially this is ok. But you've just put a 1ma load on a fully depleted cell! along with the 0.5ma gate drive load of R4 it's going to continue to discharge the battery, how long will it last? At some point the cell voltage will fall low enough that insufficient current will flow through the LED and the gates of Q2-Q3 will turn on again reconnecting the load and fully discharge the cell to 0V damaging it. So at what point will this happen? In a 16 Cell battery lets assume the other cells are at 3v, that's 48V on the the pullup R4 to the gates of Q2-Q3. The opto has to pull that 100k to ground, so it needs to flow almost 500uA. If you have a worst case current transfer ratio of the optoisolator of 100% you'll need to flow 500uA into that optocoupler to keep the gates from turning on. The drop across the LED is maybe 1.2V, the drop across the TC54 output is maybe 0.1V, but as the cell voltage drops this starts to go up fairly rapidly since the gate voltage inside the TC54 is also dropping, say it gets to 0.2V. We need 0.4V across our 820 resistor to keep things working, but that means that somewhere in the range of 1.8V of cell voltage the LVC system stops working and the FETs turn on and discharge the cell to 0V and destroy it. If somebody runs a pack down to cutoff and doesn't recharge it soon.....
ouch
kbarrett
10 kW
Randomly said:
So ... Goodrum's LVC is safe only if it is plugged in to the battery while the battery is in use, in your opinion?
Is there a quick and easy way to resolve this off-use current leak with the current board? Maybe a 0.5V watch battery soldered to run current to the resistor in question? Would a battery comprised of cells that will never get near 1.8V, like an A123 with an cut-off value of 2.7V, be safe here?
If you rode the pack until the LVC came on, you would want to recharge it immediately upon return to charger.
If you were storing it for a long time (winter), you would want to unplug the BMS from the pack.
If you were storing it for a long time (winter), you would want to unplug the BMS from the pack.
disadvantage
100 W
- Joined
- May 23, 2007
- Messages
- 126
If you know a better way, then show us. That's what the forum is here for.Randomly said:
Keep in mind we use large cells with large loads, so an optocoupler drain isn't much in an overall ebike system.
In fact, I suspect cell self-discharge is higher than the LVC drain.
I had a fully charged lipo pack sit all this past winter; this pack does not have a BMS connected to it. See "My Ride" in my sig.
Over 3 months it self-discharged (without a BMS) enough to require several hours of charging & balancing to prepare for spring riding.
The cells did *not* discharge down to 0V, and the pack is not damaged. I'll be riding home tonight with this pack.
in response to the laundry list from a new member:
if you look at the data sheet for the CD4538 you will find that the capacitor cannot discharge through the timing pin on power down, so there is no extra protection required. I do listen to criticism, but this is one case where you are laying it on without doing your homework. You will also find that pulse widths up to infinity are programmable and that pulse accuracy is very good. Perhaps you were thinking of the ttl part not the cmos? from the CD4538 data sheet:
The CD4538BC is a dual, precision monostable multivibrator
with independent trigger and reset controls. The device
is retriggerable and resettable, and the control inputs are
internally latched. Two trigger inputs are provided to allow
either rising or falling edge triggering. The reset inputs are
active LOW and prevent triggering while active. Precise
control of output pulse-width has been achieved using linear
CMOS techniques. The pulse duration and accuracy
are determined by external components RX and CX. The
device does not allow the timing capacitor to discharge
through the timing pin on power-down condition. For this
reason, no external protection resistor is required in series
with the timing pin. Input protection from static discharge is
provided on all pins.
the oneshots were tacked on as an afterthought because gary wanted the cells to sit at 3.65v for some period of time after all the cells got there, but that requirement will probably go away and with it the need for the one shots at all.
your claim that a 6.2v zener does not protect the gate of the irfb4110 is nonsense. the part can handle +/- 20V gate to source. Another case where if you looked at the data sheet you would know what you are talking about.
i have been very clear all along that the LVC cutoff does not protect the pack sitting on the shelf for months against over discharge. it is intended to be a warning while under power that the pack needs to be charged. the TC54 draws 1 MICROAMP so it will not be dragging the pack down very quickly, and the control circuit is only powered when the charger is connected. if you let your pack sit around for a few weeks after getting the LVC error yes it may be damaged. The rate of self discharge is bound to be much more than the microamp the TC54 draws. Another case where if you looked at the data sheet you would know.
i came up with the design in response to requests from gary, it started as just the LVC portion, and it works fine. The rest of the circuitry evolved over time, and i have not kept the original released schematic up to date, so a couple of your issues are not actually there, like the zener on the gate of the fet which is actually supposed to be 5.1v not 6.2 as the drawing shows.
if you spent half the time designing your own bms that you spent finding fault with mine you might have a workable system yourself and people will flock to your door. once again, the circuit posted is the first cut and does not really reflect what is going on the board at present. i have tested 500 of the optic isolators i am using and the minimum CTR i have found is 200%, so that answers another of your issues. the truth is that when one cell hits LVC another cell will likely not be far behind, so if the first one does not pull down the control signal the second one will.
If you want to make suggestions or ask questions i and other people are happy to listen, but when you come off like a sarcastic know it all most people will not read past the first few lines. I know i won't. a little knowledge is a dangerous thing, and your criticism is full of assumptions, and you know what they make...
if you look at the data sheet for the CD4538 you will find that the capacitor cannot discharge through the timing pin on power down, so there is no extra protection required. I do listen to criticism, but this is one case where you are laying it on without doing your homework. You will also find that pulse widths up to infinity are programmable and that pulse accuracy is very good. Perhaps you were thinking of the ttl part not the cmos? from the CD4538 data sheet:
The CD4538BC is a dual, precision monostable multivibrator
with independent trigger and reset controls. The device
is retriggerable and resettable, and the control inputs are
internally latched. Two trigger inputs are provided to allow
either rising or falling edge triggering. The reset inputs are
active LOW and prevent triggering while active. Precise
control of output pulse-width has been achieved using linear
CMOS techniques. The pulse duration and accuracy
are determined by external components RX and CX. The
device does not allow the timing capacitor to discharge
through the timing pin on power-down condition. For this
reason, no external protection resistor is required in series
with the timing pin. Input protection from static discharge is
provided on all pins.
the oneshots were tacked on as an afterthought because gary wanted the cells to sit at 3.65v for some period of time after all the cells got there, but that requirement will probably go away and with it the need for the one shots at all.
your claim that a 6.2v zener does not protect the gate of the irfb4110 is nonsense. the part can handle +/- 20V gate to source. Another case where if you looked at the data sheet you would know what you are talking about.
i have been very clear all along that the LVC cutoff does not protect the pack sitting on the shelf for months against over discharge. it is intended to be a warning while under power that the pack needs to be charged. the TC54 draws 1 MICROAMP so it will not be dragging the pack down very quickly, and the control circuit is only powered when the charger is connected. if you let your pack sit around for a few weeks after getting the LVC error yes it may be damaged. The rate of self discharge is bound to be much more than the microamp the TC54 draws. Another case where if you looked at the data sheet you would know.
i came up with the design in response to requests from gary, it started as just the LVC portion, and it works fine. The rest of the circuitry evolved over time, and i have not kept the original released schematic up to date, so a couple of your issues are not actually there, like the zener on the gate of the fet which is actually supposed to be 5.1v not 6.2 as the drawing shows.
if you spent half the time designing your own bms that you spent finding fault with mine you might have a workable system yourself and people will flock to your door. once again, the circuit posted is the first cut and does not really reflect what is going on the board at present. i have tested 500 of the optic isolators i am using and the minimum CTR i have found is 200%, so that answers another of your issues. the truth is that when one cell hits LVC another cell will likely not be far behind, so if the first one does not pull down the control signal the second one will.
If you want to make suggestions or ask questions i and other people are happy to listen, but when you come off like a sarcastic know it all most people will not read past the first few lines. I know i won't. a little knowledge is a dangerous thing, and your criticism is full of assumptions, and you know what they make...
GGoodrum
1 MW
I'll leave the rest of the BMS questions for Bob, but I will take a whack at the LVC issues. The TC54 only draws about 10 uA, when the voltage is above the 2.1V cutoff. that by itself would take years to discharge a cell any appreciable amount. On the LVC-only boards, with the active cutoff portion populated, there are only the two FETs, a 5.1V Zener and a 100k pullup resistor. If there is no other load on the pack left on, there is no way I can see this being able to drain the pack dead, at least in my lifetime. :wink:
The way the LVC board normally works, when the pack is drained down, at some point under load one or more cells will trip their LVC circuit, which cause the load to be instantly removed. This causes the cells to recover, usually to well above 3.0V per cell. If the load is still there, it will "hit" again, repeatedly until the throttle is backed off, so that the load causing the voltage drop is reduced enough to keep all the cells above the cutoff. When I first notice the first hit, it is usually while giving it full throttle, going up a hill. It hits, like a big trout. If I don't reduce the throttle, it'll hit again, about a half second to a second later. If I reduce the throttle to about half, I can actually go another couple of miles before it finally starts oscillating on and off. At that point, the resting voltage is still a bit above 3V per cell. Even leaving the LVC connected, it is going to take an awfully long time to drain the cells until they get to 2.1V. I can't imagine that it wouldn't last a winter, but I would never leave a pack drained for months at a time anyway. It is always better to fully charge packs that will be left on the shelf for an extended period of time.
In any case, I always leave my LVC boards connected to the packs, and have not had a single problem. The boards do have multipin connectors, so I could unplug the packs, if I wanted to, but I don't see the point. If I had a case where the LVC was cutting out way beofre it should, which would indicate a possible problem with a bad cell perhaps, I'd then disconnect the LVC board, but that is so I can address the problem. I'd never continue to use a pack that has the LVC cutting out too soon, without finding out the cause.
-- Gary
The way the LVC board normally works, when the pack is drained down, at some point under load one or more cells will trip their LVC circuit, which cause the load to be instantly removed. This causes the cells to recover, usually to well above 3.0V per cell. If the load is still there, it will "hit" again, repeatedly until the throttle is backed off, so that the load causing the voltage drop is reduced enough to keep all the cells above the cutoff. When I first notice the first hit, it is usually while giving it full throttle, going up a hill. It hits, like a big trout. If I don't reduce the throttle, it'll hit again, about a half second to a second later. If I reduce the throttle to about half, I can actually go another couple of miles before it finally starts oscillating on and off. At that point, the resting voltage is still a bit above 3V per cell. Even leaving the LVC connected, it is going to take an awfully long time to drain the cells until they get to 2.1V. I can't imagine that it wouldn't last a winter, but I would never leave a pack drained for months at a time anyway. It is always better to fully charge packs that will be left on the shelf for an extended period of time.
In any case, I always leave my LVC boards connected to the packs, and have not had a single problem. The boards do have multipin connectors, so I could unplug the packs, if I wanted to, but I don't see the point. If I had a case where the LVC was cutting out way beofre it should, which would indicate a possible problem with a bad cell perhaps, I'd then disconnect the LVC board, but that is so I can address the problem. I'd never continue to use a pack that has the LVC cutting out too soon, without finding out the cause.
-- Gary
GGoodrum said:
actually it is only 1 microamp not 10, so 10x as long to discharge. basically not an issue. the other constant drain is the 100k pot plus 150k resistor that are across the cell in the complete bms, so this adds another 15 microamps drain that is not there on the LVC only version. this is still well below the self discharge rate.
another issue raised was the input offset of the lm358a and the claim was made that it has 7 mv offset. this may be the absolute maximum offset for the lower grade parts from -50 to +125C, but the part will never see those temperature extremes in this application. the parts i am using are 2 mv typical offset, and in effect that is adjusted out with the pot that sets the final charge phase current. if the offset drifts a bit it will just change the current slightly during the final balancing phase of the charge cycle, so this too is a non-issue. All it would mean is that the time to reach full charge might vary slightly.
I'll give you the discharge protection on the CD4538 if you are using the Fairchild part. However this is not true of 4538 of all manufacturers, TI for one requires protection.
Sure theoretically the 4538 would operate with any length pulse widths. However you have to deal with real world components. Please go look up what the worst case leakage of your 1000uF cap is. My point was the leakage of the cap can far exceed the pullup current available from the resistor and the circuit will never reach the trip point.
I'm not arguing about the current drain of the LVC circuit before the pack hits the cutoff. It's almost irrelevant, even a few milliamps with a 10,000 mah pack lasts a long time. However the current drain after the pack hits LVC cutoff is crucially important and that is where you increase the drain to about 1.5ma.
When the LVC trip point is hit, you no longer have a huge AH capacity battery, the battery capacity is now relatively tiny.
Go look at the discharge curves on a 10AH cell and tell me how many mah of capacity are left in the cell after it hits the 2.1V cutoff? Maybe as little as 50-100mah. The curve at that point is extremely steep. How many hours at 1.5ma will it take till the voltage falls to the point where the LVC stops working and reconnects the load? It may only be a couple days. Don't forget the R4 load which never goes away, which will be about 500uA with a 16cell pack.
You misunderstand my objection to your 6.2V zener as gate protection. Certainly it will protect the gate oxide from punch through. My point was that the 6.2V gives too low a gate voltage. The worst case Vgs threshold is 4v, this increases with decreasing temperature. A 6.2V gate drive is so close to this that at high currents the channel may start to pinch off putting the FET in the linear region. This will increase the voltage drop across the FET tremendously and the high current and voltage drop = HUGE power and you'll toast your FET in a heartbeat. This is easily solved by increasing this zener to 10-12Volts. Also increasing the gate voltage will reduce the FET on resistance considerably from a 6v gate drive and may reduce power dissipation in those FETs by half. Go back and look at the IRFB4110 spec sheet, it's all based off 10V gate drives.
You cannot increase the Gate voltage however without fixing the Q6 problem. A 10-12 volt gate voltage will certainly exceed the breakdown voltage of the BE junction of Q6, this will pull the gate of Q4 up and you will be unable to turn the charging current down or off.
Even with a 200% CTR (which you can't necessarily count on in production, never design to typical specs) it only means the cell voltage needs to fall another 200mv before the LVC fails. The current drains are still there, and the failure mechanism is still there.
I'm sorry if I come across to you as sarcastic and are taking these comments harshly. It's easy to misread intent and meaning in purely text based communication. Every one of these points I've raised is valid, please consider them carefully and I hope they will help you. I'm not interested in designing a BMS to sell, and I only spent an hour or so going over your schematic out of interest.
Sure theoretically the 4538 would operate with any length pulse widths. However you have to deal with real world components. Please go look up what the worst case leakage of your 1000uF cap is. My point was the leakage of the cap can far exceed the pullup current available from the resistor and the circuit will never reach the trip point.
I'm not arguing about the current drain of the LVC circuit before the pack hits the cutoff. It's almost irrelevant, even a few milliamps with a 10,000 mah pack lasts a long time. However the current drain after the pack hits LVC cutoff is crucially important and that is where you increase the drain to about 1.5ma.
When the LVC trip point is hit, you no longer have a huge AH capacity battery, the battery capacity is now relatively tiny.
Go look at the discharge curves on a 10AH cell and tell me how many mah of capacity are left in the cell after it hits the 2.1V cutoff? Maybe as little as 50-100mah. The curve at that point is extremely steep. How many hours at 1.5ma will it take till the voltage falls to the point where the LVC stops working and reconnects the load? It may only be a couple days. Don't forget the R4 load which never goes away, which will be about 500uA with a 16cell pack.
You misunderstand my objection to your 6.2V zener as gate protection. Certainly it will protect the gate oxide from punch through. My point was that the 6.2V gives too low a gate voltage. The worst case Vgs threshold is 4v, this increases with decreasing temperature. A 6.2V gate drive is so close to this that at high currents the channel may start to pinch off putting the FET in the linear region. This will increase the voltage drop across the FET tremendously and the high current and voltage drop = HUGE power and you'll toast your FET in a heartbeat. This is easily solved by increasing this zener to 10-12Volts. Also increasing the gate voltage will reduce the FET on resistance considerably from a 6v gate drive and may reduce power dissipation in those FETs by half. Go back and look at the IRFB4110 spec sheet, it's all based off 10V gate drives.
You cannot increase the Gate voltage however without fixing the Q6 problem. A 10-12 volt gate voltage will certainly exceed the breakdown voltage of the BE junction of Q6, this will pull the gate of Q4 up and you will be unable to turn the charging current down or off.
Even with a 200% CTR (which you can't necessarily count on in production, never design to typical specs) it only means the cell voltage needs to fall another 200mv before the LVC fails. The current drains are still there, and the failure mechanism is still there.
I'm sorry if I come across to you as sarcastic and are taking these comments harshly. It's easy to misread intent and meaning in purely text based communication. Every one of these points I've raised is valid, please consider them carefully and I hope they will help you. I'm not interested in designing a BMS to sell, and I only spent an hour or so going over your schematic out of interest.
GGoodrum
1 MW
Again, I'll let Bob address your BMS design points. For the LVC, however, I have probably more experience in using these boards than anybody, and there just isn't anyway that what you will describe will happen in the real world. First of all, you missed the point that the LVC first trips when the pack is under load. As soon as the load is removed, the cells bounce back to well over 3.0V per cell. I have monitored the Ah used, when this first happens, and for all of my LiFeBatt packs,, there is about 9.20-9.30 Ah used, out of 10Ah total capacity. If I keep using the pack down to the point that even giving it a slight bit of throttle will casuse the cutout oscillations, the amount of Ah used goes up to about 9.80-9.85 Ah. I have tried this without any LVC protection and have drained as much as 10.20 Ah. I get the same sort of numbers with all of my a123 packs, but with them, I use the 2.7V version of the TC54.
It would not be wise to take a depleted pack, and put it on the shelf for 3 months, but even if you did, at 1uA, it would take a helluva lot longer than a couple of months to drain 100mA out of the pack. If I did the math right, it is like 10,000 hours, which is 416 days, or well over a year.
The bottomline is you are just never going to find anybody that is going to put a drained pack on the shelf for 2-3 months. That is just nonsense.
-- Gary
It would not be wise to take a depleted pack, and put it on the shelf for 3 months, but even if you did, at 1uA, it would take a helluva lot longer than a couple of months to drain 100mA out of the pack. If I did the math right, it is like 10,000 hours, which is 416 days, or well over a year.
The bottomline is you are just never going to find anybody that is going to put a drained pack on the shelf for 2-3 months. That is just nonsense.
-- Gary
GGoodrum
1 MW
Also, I know for a fact that the schematic you are looking at is nowhere near current. Here is the last one I did:
View attachment LiFeCycle BMS-v1 14.png
View attachment LiFeCycle BMS-v1 14.png
You are focusing on the TC54 current drain when the pack is above cutoff. The current drain is not from the TC54 but the rest of the circuit.
Calculate how much current drain that depleted cell has on it when the TC54 has triggered and pulled the output low turning on the Opto isolator? also add in the current drain through the 100k pullup resistor on the gates of Q3 and Q4 ( I can't read the designator on your latest schematic). How much current is that total? it's more in the range of 1500uA, not 1ua.
What if somebody forgets and leaves their motor controller on, or some other load attached to the battery? Your circuit won't protect against that. The battery is depleted till the cutoff point, then a few days later the LVC stops working and the FETS turn on again and the battery is fully depleted. You can't count on people never forgetting stuff like that and these are EXPENSIVE things to lose. Basically any low to moderate load and you are potentially in trouble.
Calculate how much current drain that depleted cell has on it when the TC54 has triggered and pulled the output low turning on the Opto isolator? also add in the current drain through the 100k pullup resistor on the gates of Q3 and Q4 ( I can't read the designator on your latest schematic). How much current is that total? it's more in the range of 1500uA, not 1ua.
What if somebody forgets and leaves their motor controller on, or some other load attached to the battery? Your circuit won't protect against that. The battery is depleted till the cutoff point, then a few days later the LVC stops working and the FETS turn on again and the battery is fully depleted. You can't count on people never forgetting stuff like that and these are EXPENSIVE things to lose. Basically any low to moderate load and you are potentially in trouble.
Randomly said:
I am not an electronics geek, so I really don't know if there is a right or wrong position. or if it is simply a matter of perspective.
However, rather than simply finding fault, can you offer an alternative solution ?
I think I can see things from both sides of the fence, I agree with Garry that it is highly unlikely that anybody who is going to ante up the dollars for a big lump of Lithium is going to choose to mistreat them and leave them in a discharged state. I also agree that the voltage sag under load causing the LVC to trip _should_ be enough of an indicator to the rider to cut the battery some slack and stop floggin it to death. THis ought to leave enough residual capacity that you could leave it at least a couple of days and not risk damage. But again, this assumes you have a conciencious operator.
As Bob so eloquently put it, when you assume....
So my 2.2 cents worth; if it is practical, you need to consider the lowest common denominator and make the BMS as idiot proof as possible. In the context of intelligent experimenters you are right to assume your operator will do everything in their power to look after their expensive battery, hell, that is precisely why they have bought your excellent BMS in the first place. And as long as there is basically a checklist for how to operate the BMS, including an explanation WHY, you should be good.
In the long term, once eBikes become 'normal' like cars and every tom dick and harry is riding one. You have a different demographic of operators and in this situation the BMS really needs to be foolproof and bullet proof. I accept you can not guard against intentional misuse, but everything possible needs to be done to prevent Joe average from screwing up his batteries.
GGoodrum
1 MW
You are not getting my point either. The reason that I'm only concerned about when the voltage is above the TC54's cutoff is because after the first time any of them tri, and you remove the load, the cells will bounce back to somewhere north of 3.0V. At 1uA, it will still take an eternity for the cells to get down below 2.1V, from something over 3.0V. You keep assuming that the cells just gradually reduce, not considering that with real packs, on real bikes, it simply doesn't work this way.
The bare-bones version of the LVC board doesn't have FET positions populated, instead, it uses the controller's ebrake line to cut the throttle. Basically, all the opto outputs are ganged together, and connected to the ebrake line and the controller ground. When any LVC circuit trips, the ebrake line is pulled down, which causes the controller to kill the throttle. For these setups, there are just the three parts for each channel, the TC54, the opto and the 820 ohm resistor. Here's what the LVC board layout looks like:
As for leaving the controller on, I don't know. I've never heard of anyone here doing that, and leaving it on for an extended period, like over winter?
I'm not sure any BMS/LVC design I've seen will protect against a bonehead move like that.
All I know is that there are at least 50-60 of the various LVC boards out there and I have yet to have a single one returned, or have anyone have anyone send me a complaint. Simply put, they work as intended, nothing more, nothing less.
-- Gary
The bare-bones version of the LVC board doesn't have FET positions populated, instead, it uses the controller's ebrake line to cut the throttle. Basically, all the opto outputs are ganged together, and connected to the ebrake line and the controller ground. When any LVC circuit trips, the ebrake line is pulled down, which causes the controller to kill the throttle. For these setups, there are just the three parts for each channel, the TC54, the opto and the 820 ohm resistor. Here's what the LVC board layout looks like:
As for leaving the controller on, I don't know. I've never heard of anyone here doing that, and leaving it on for an extended period, like over winter?
I'm not sure any BMS/LVC design I've seen will protect against a bonehead move like that. All I know is that there are at least 50-60 of the various LVC boards out there and I have yet to have a single one returned, or have anyone have anyone send me a complaint. Simply put, they work as intended, nothing more, nothing less.
-- Gary
Randomly said:
so if the drain goes up to a couple of ma that means that in about 3 weeks you will lose 1 Ah. what actually happens is that as soon as the load is removed the battery voltage rises, so the LVC is negated and the drain returns to microamps. My tests have shown that there is about 10% capacity typically remaining when the LVC trips, so yes i do not recommend letting the battery sit in the discharged condition for weeks.
you are absolutely incorrect that there is only 1% of the capacity left in a 10 Ah pack after the first time a cell hits 2.1v (or 2.7v for a123). as i have stated it is at least 10x that. you are ignoring the voltage drop due to the battery internal impedance that causes the voltage to dip to 2.1v while at 30A and .005 ohms is actually 2.25v cell voltage
Randomly said:
i have looked at the curves, and i am aware of the self discharge characteristics. if you think a half a milliamp is too much disconnect the bms when you are going to let your dead battery sit on the shelf. i always charge mine asap.
Randomly said:
here once again you are not really looking at the numbers or considering the function. the irfb4110 will be operated in the linear mode during the reduced charge current phase, and is driven up above 4.5v when full on, and that is plenty of voltage to turn on the fet completely under all forseen conditions.
i knew that when i posted the schematic it was likely there would be people who wanted to pick it apart. go for it. i dont have time to argue any more irrelevant issues.
Randomly said:
i did not mean to be harsh, i just dont have time to argue engineering with every newcomer. if you dont like the design dont buy one. i am really beginning to doubt that selling them can be profitable anyway, so you may never get the chance. i did not set out to design a product for sale. i just needed one bms for a lifebatt pack i sold (the only one) and lifebatt did not come through. I did not spend as much time as i should have for a production design, but when i only have the stamina to work an hour or two a day this is what we get. I have a steady stream of controllers to repair that i can make about $25 an hour at, so forgive me if i focus on that and dont have time to argue about operation of components outside the design parameters.
some of your points may be valid, but you will get a much better response if you avoid phrases like "what were you thinking?" and maybe replacing them with "it might be better to...". Certainly there is leakage in the electrolytic caps but it is not high enough that it does more than extend the time past the predicted RC value, and the timing was only meant to be approximate anyway. most likely the charger will just be cut off as soon as all the cells reach the shunt voltage and the one shot will go away. the long time delay was only intended to give the user time to disconnect the charger before it restarts and initiates a short charge cycle. it could be replaced with a latch and reset mechanism. i have been using the 4110s for quite some time and have had no problems with driving the gates to 5-6v and expecting them to handle all the current i need. i will take a look at the consequences of driving the gate voltage higher to the other parts of the circuit, it is a good suggestion just to guarantee performance over a wide range of temperature and current.
I was not referring to the 6.2V gate drive on the charger current limiter FET but on the output load FETs Q3 and Q4. These can experience much higher currents.
ok, I will respond to the suggestion of offering a better solution. Here is a go at an LVC circuit using your TC54.
ok, I will respond to the suggestion of offering a better solution. Here is a go at an LVC circuit using your TC54.
I may have the pin outs wrong on the TC54, I just slapped this together. This drawn up for 7 cells but you can scale it up or down as you like.
This circuit should pull essentially NO current from a depleted cell when that cell goes low enough to turn set off its TC54, except for the quiescent current of the TC54. D1-D6 are schottky diodes, you will need to pick one with low reverse leakage such as MBD77DWT1 or some such. Quiescent current when the output FET is on should be less than about 200uA. The values are just a starting point, you can fiddle with them to lower the current or raise them to decrease turn on time of the FETS.
Q9 and Q10 form an SCR like circuit with positive feedback that Slams the gate of the output FET off very fast. You don't want the FETs to turn off slowly under heavy load. Q8 accelerates turn on times by multiplying the output current out of Q7 by it's beta, but doesn't increase quiescent current. Q7 and Q8 need to handle the full pack voltage so pick your parts accordingly. The other transistors are fairly noncritical although Q9 and Q10 should be higher current (600ma) types.
This circuit
1) Should protect the pack from being overdrained under any condition, such as loads or controllers being left on or something shorted etc.
2) will not turn on if a cell voltage is below the cutoff no matter how low the cell voltages get.
3) Has several times less quiescent current when on
4) Has much faster turn on and off times
5) Will not slowly drag the output FET gate through the linear region which may happen with your opto pull downs.
6) it's probably cheaper to make to.
Now I just drew this up, and I haven't tried it. So there may be something I missed or messed up, but I think it's a decent start in the right direction.
This circuit should pull essentially NO current from a depleted cell when that cell goes low enough to turn set off its TC54, except for the quiescent current of the TC54. D1-D6 are schottky diodes, you will need to pick one with low reverse leakage such as MBD77DWT1 or some such. Quiescent current when the output FET is on should be less than about 200uA. The values are just a starting point, you can fiddle with them to lower the current or raise them to decrease turn on time of the FETS.
Q9 and Q10 form an SCR like circuit with positive feedback that Slams the gate of the output FET off very fast. You don't want the FETs to turn off slowly under heavy load. Q8 accelerates turn on times by multiplying the output current out of Q7 by it's beta, but doesn't increase quiescent current. Q7 and Q8 need to handle the full pack voltage so pick your parts accordingly. The other transistors are fairly noncritical although Q9 and Q10 should be higher current (600ma) types.
This circuit
1) Should protect the pack from being overdrained under any condition, such as loads or controllers being left on or something shorted etc.
2) will not turn on if a cell voltage is below the cutoff no matter how low the cell voltages get.
3) Has several times less quiescent current when on
4) Has much faster turn on and off times
5) Will not slowly drag the output FET gate through the linear region which may happen with your opto pull downs.
6) it's probably cheaper to make to.
Now I just drew this up, and I haven't tried it. So there may be something I missed or messed up, but I think it's a decent start in the right direction.
thanks for the positive suggestion. i will take a closer look at it tomorrow when i am fresh and see if i agree it is worth all the extra components. if the only goal is to drive the fet gate higher the optos will take 70v, and they may be less expensive than the approach you suggest. the optos permit the design to be easily adjusted to virtually any number of cells. a quick glance indicates that may not be true for your first cut, but designs can always be improved.
this late in the day my pain meds start to wear off, so forgive me if i am a bit grouchy. my goal is to help my fellow ebikers get better performance from their batteries. any input in that direction is appreciated. i have made lots of mistakes and will make many more, that's why engineering reviews are conducted in the real world.
this late in the day my pain meds start to wear off, so forgive me if i am a bit grouchy. my goal is to help my fellow ebikers get better performance from their batteries. any input in that direction is appreciated. i have made lots of mistakes and will make many more, that's why engineering reviews are conducted in the real world.
PJD
100 W
Randomly,
I don't pretend to have a grasp on all the technical issues, but you should understand that most us won't be using the BMS to switch the the pack power off at all. (It would be up to 95 amps worth in my case). The LVC logic signal will be used directly wit h the brake-cutoff (the "e-brake" as Gary calls it) or the throttle signal that all bike or motorcycle controllers use. Q3 and Q4 will be left off the board altogether. True, I won't have battery protection against, say leaving my keys in the scooter and switched on for several days - but other things, like theft, are bigger threats in such situations.
I don't pretend to have a grasp on all the technical issues, but you should understand that most us won't be using the BMS to switch the the pack power off at all. (It would be up to 95 amps worth in my case). The LVC logic signal will be used directly wit h the brake-cutoff (the "e-brake" as Gary calls it) or the throttle signal that all bike or motorcycle controllers use. Q3 and Q4 will be left off the board altogether. True, I won't have battery protection against, say leaving my keys in the scooter and switched on for several days - but other things, like theft, are bigger threats in such situations.
