New TI BMS chipset?

[dogzapper]

Glad to find this thread (and web site!), this is some good stuff. I got my bq78pl114 eval card yesterday. Unfortunately, it did not contain a complete kit. My USB dongle board was missing. I'm suppose to get it tomorrow. I can't wait to get started.

My initial design will be a 4S5P LiFePO4 pack. Anyone have experience using 5P or more with the bq78pl114? My big concern right now is safety, what happens if one of my 20 cells shorts out and starts to overheat? Will the bq78pl114 stop a run away melt down or do I need to design in other protection devices to protect against this fault condition? How likely is a spontaneous less-than-full charge cell short-out condition? Right now, I plan on my max charge voltage to be about 3.4vpc, so my pack will never hit full charge but this should be OK in my application.

Has anyone read the TI application report SLUA495A - Configuring the bq78PL114 Cell Count...? I did the math...and with my cell capacity and other stuff...the maximum number of parallel cells could be 46? That seems a little hard to believe...?

 

[CamLight]

reagle,
Good news that it's balancing better. I've had great luck with the 400 chemistry and the A123 cells, consistently balancing even if set to a diff of 5mV.

But, I had the same problem you're having. I had to increase the Cell Undervoltage (CUV), Pack Undervoltage (PUV) and Discharge Completion voltages for the pack I'm working with in order to keep them balanced all the way to the end of discharge. Typically, they stay within 15mV-20mV or so of each other and balancing is finished in a coupe of minutes of the Discharge Complete (DC) signal turning on. Before, I could get a 100mV range between cells at high discharge current levels. Currently, I have the following for a 4S1P pack:

DC voltage = 11,600
TDA set voltage = 11,800
FD set voltage = 10,800
PUV = 11,200
CUV = 2,700

From my balancing reading, I decided to limit the SOC range the cells would operate in. This has really made a difference in how well the packs stay balanced during chg/dischg. By stopping at 3.6V on chg and 2.9V on dischg, I can stay very nicely balanced. Every time I try to take it up to a "full" charge (about 3.74V on this pack) or a "full" discharge down to 2.7V-2.8V, I get big voltage variations between cells. Nothing really there, in terms of charge, above 3.6V or below 2.9V so I'm not too worried.

But, I have had FCC go to zero when changing to a discharge current level that I haven't used recently. I cycled a pack at 1A chg/1A dischg three times for the chip to do all its calculations and then tried a 15A discharge. The FCC, Rem. Cap., Rel, SOC, Abs. SOC, and Time to Empty all went crazy. They either said xero or 65535.

I don't know if this is the Cell Chemistry's Capacity Algorithm making it go crazy (Set to Average Current) or what, but I'll have to do more testing. Having the SOC LEDs indicate 80%-100% after completing a full discharge (DC indicator lit) is not a good thing!

Do you let your pack rest for 30+ minutes after a charge/discharge to update the Idle OCV? Does this affect the FCC indicator?

 

[CamLight]

Glad to find this thread (and web site!), this is some good stuff. I got my bq78pl114 eval card yesterday. Unfortunately, it did not contain a complete kit. My USB dongle board was missing. I'm suppose to get it tomorrow. I can't wait to get started.

My initial design will be a 4S5P LiFePO4 pack. Anyone have experience using 5P or more with the bq78pl114? My big concern right now is safety, what happens if one of my 20 cells shorts out and starts to overheat? Will the bq78pl114 stop a run away melt down or do I need to design in other protection devices to protect against this fault condition? How likely is a spontaneous less-than-full charge cell short-out condition? Right now, I plan on my max charge voltage to be about 3.4vpc, so my pack will never hit full charge but this should be OK in my application.

Has anyone read the TI application report SLUA495A - Configuring the bq78PL114 Cell Count...? I did the math...and with my cell capacity and other stuff...the maximum number of parallel cells could be 46? That seems a little hard to believe...?

Just 4S1P and 4S2P here.
If you don't have individual cell fusing, and one cell decides to go, all the cells in that parallel string will go with them. And probably the adjacent series cells too. Limiting the operating temperature, voltages, and current levels will do a lot towards making sure that never happens though. But, it's still possible.

Roughly, the max number of parallel cells is (32,000mAh) / (capacity per cell). What is the capacity of your cells?
You also have to make sure the numbers work out for the design energy calculations too:

Max # of parallel cells < (65,535 x 10) / ((cell cap in mAh)) x (# of series cells) x (nominal cell voltage))

 

[CamLight]

I may have solved the wandering FCC and Remaining Cap. problem. I was using a Capacity Algorithm setting of 3, which is Average Current. Since my current levels are changing from less than 1A to over 100A, randomly, I changed the algorithm to 1, Present Current. So far, so good. More testing to come.

 

[CamLight]

Update- moved to S12 firmware and enabled turbo balancing with max duty cycle. Now it seems to balance better, but the moment I hit the pack with the load inevitably one cell drains down faster than the rest. Same on charge- I always hit OCV on a cell before the rest. That's despite the cells being pretty much at the same voltage before that. Weird..I wonder if it's the fact that cells sat for a while in a 2P pack and are now in 1P

I forgot to mention this...
Switch to SOC balancing. It does a better job of keeping the cells balanced as they're charged or discharged. You're still limited to a 5%-95% SOC range (best case, could be 20%-80% depending on cell condition) to keep balanced, but it gives better results than just using OCV to balance.

Google "SOC balancing" or "State of charge balancing" for some great white papers by Intersil and Texas Instruments.

 

[CamLight]

reagle,
How's the EVM doing? I've been having pretty good luck with the setup so far but have also seen the varying voltage-under-load and voltage-during-charge curves for already-balanced cells in a pack. Overall, the A1223 M1 cells behave well, even at 15C discharges, but every once in a while one cell goes off on its own (up to 150mV off from the others) and I get a COV or CUV alarm and the FETs turn off before the discharge or charge is complete. The pack always balances back up again, but it's strange.

I was about to do the 78PL114S12 conversion (new firmware, 1mohm sense resistors, removing the temp sensor multiplexing) since I need to handle over 100A discharges and was wondering if you had any problems when you did your conversion?

 

[reagle]

We did mod one board to run S12 firmware and it went well. Just needed to follow the instructions carefully. Also gotta make sure you use the correct settings files (from S12 folder, not the regular one). Balancing did seem to improve a bit, but I still had half of a pack balanced to itself and the other half balance to self, with quite a bit of a difference between the two.
Ended up switching to a Linear Tech demo board with LTC6802 and running a few charge discharge cycles manually. The pack is now nicely balanced, though I do not get the nice state of charge info TI chips provide. I did note how much more bulletproof LTC6802 EVM seems to be- I only have one but it's been working no matter what I threw at it. That does seem to describe Linear Tech parts in general though

reagle,
How's the EVM doing? I've been having pretty good luck with the setup so far but have also seen the varying voltage-under-load and voltage-during-charge curves for already-balanced cells in a pack. Overall, the A1223 M1 cells behave well, even at 15C discharges, but every once in a while one cell goes off on its own (up to 150mV off from the others) and I get a COV or CUV alarm and the FETs turn off before the discharge or charge is complete. The pack always balances back up again, but it's strange.

I was about to do the 78PL114S12 conversion (new firmware, 1mohm sense resistors, removing the temp sensor multiplexing) since I need to handle over 100A discharges and was wondering if you had any problems when you did your conversion?

 

[CamLight]

I have the LTC demo board too but love the balance-all-the-time feature, the SOC data, and the lack of heat of the TI setup. Hopefully, it keeps working out well for us.

Any feedback from TI on what the problem might be with balancing your pack? I would think that having the right chemistry file for the pack is important only when first using the pack and that it wouldn't matter once you did a few cycles. Especially since the balancing stuff is just voltage reading, nothing to do with the chemistry....it seems. Glad the LTC board is working well for you though!

Thanks for the update on your S12 conversion. I'll make sure I follow the instructions carefully. I have the Rev3 board so there are several changes to make. And thanks for the S12 folder tip! That would be an easy mistake for me to make.

 

[CamLight]

The pack is now nicely balanced, though I do not get the nice state of charge info TI chips provide.

Did you ever notice any resetting-to-zero of the Abs SOC and Rel SOC parameters when discharging at higher current levels? When doing 5A/5A chg/dischg cycling, everything reads OK. But, when we do 5A/15A cycles, the darn capacity and SOC parameters have useless info or are zero until we fully charge again.

 

[reagle]

I did ask and got no answer as far as balancing.
I do not recall seeing SOC drop to 0, but I was also not too concerned with it, since I never actually configured the chemistry correctly to begin with.
Cycling with "regular" cobalt cells at 10A things behaved pretty well.
I wonder if you are getting some type of correction kicking in based on some voltages. In the older parts they did it all by EDV (End of Discharge Voltage) points. Not sure if these still do something with that

 

[CamLight]

Thanks, I think you're right.
I've done some reading and it's a pretty complex algorithm for calculating SOC and, IIRC, the chip doesn't even try doing it when the pack is in the mid-part of the SOC range due to the very flat voltage vs. SOC curve. At least it goes to a "nonsense" value when conditions have changed to a point where the chip can't very accurately track SOC. Some times I wouldn't mind a best-guess though as something like "probably 40%-60%" would be a lot nicer than "I don't know".

 

[perbear]

I have just finished my four layer BMS PCB. It uses four bq76PL102 and one bq78PL114S12 and is designed for ebikes/ULEV satisifed with up to 12 Li cells in series. If anyone is interested I will make available soldered boards with all 243 parts, or bare boards if you have a acess to your own P&P soldering line. Check it out at http://groups.google.com/group/nohassel/web/bms

 

[CamLight]

Great news perbear! I'm looking forward to checking out the board.
Frustrated that it's a closed Google group and that I had to join the group and now wait for approval though.

[Edit] Thanks for approving my membership. I'm interested in hearing how the first boards work out!

 

[CamLight]

I have just finished my four layer BMS PCB. It uses four bq76PL102 and one bq78PL114S12 and is designed for ebikes/ULEV satisifed with up to 12 Li cells in series. If anyone is interested I will make available soldered boards with all 243 parts, or bare boards if you have a acess to your own P&P soldering line. Check it out at http://groups.google.com/group/nohassel/web/bms

What did you change the PowerPump reference schematic component values to for the higher balance current? Just the inductor? Or the FETs, inductor, and caps? I only ask because, IIRC, you mentioned 150mA balancing and the reference circuit only does about 75mA to 100mA (at best).

 

[reagle]

I seem to remember TI mentioning inductor values affecting the currents, but it would probably affect everything else in the chain

 

[CamLight]

Same As I remember, the inductor is the key for increasing current.
Yea, the FET might have to be upgraded to handle the increased peak current and the cap value changed (increased to handle the increased ripple voltage?).

I checked perbear's schematic and he's using the reference schematic's part value for balancing (same as I'm doing in my board). not sure why we have different values for the average balancing current level.

He's got a gorgeous board though.

 

[perbear]

Actually, my calculations based on the formulas from TI gives a peak balancing current of 1.32A and average current of 0.22A on A123 cells. Also remember that the board have large power planes between charge capacitors (22uF) and filter caps (10uF) that was not included in the calculations and that should increase balancing current by decreasing inductance and ESR both for charging and for discharging. I have to admit that the calculation is simplified and does only include nominal values of the parts and no inductance and resistance in PCB and capacitors or other parasitic effects. Ideally I should have done a more accurate simulation, so I reduced the calculated value by 30% giving 150mA as a realistic figure.

This could be overly optimistic, but the plan is to test two boards using two different setups: Board #1 is assembled according to schematic. If it supplies 150mA or more, all is well. Board #2 is assembled with different powerpump part configurations to see how different capacitance, inductance and ESR affects balancing current.

Here is a picture of the finished boards, a high res picture can be found at the Nohassel Google group in the file section:

 

[CamLight]

Thanks for the info perbear.
I also used the reference schematic components but have only gotten about 75mA+ (avg.) balancing current flow. I've checked the PowerPump waveforms with my scope and, while they're not as clean as the ones shown in the TI docs, they looked "good enough". I guess not.

My balancing current level does match the value mentioned in Section 3.9 of the System Design Guidelines document though so I probably shouldn't be too upset. Was just hoping to get closer to the theoretical value since my layout had, what I hoped was, much lower trace resistance/inductance and used lower Rds-on FETs than the reference design.

I haven't played with the PowerPump duty cycle adjustments in the firmware yet. That should help some. I can deal with the less-frequent temperature checking that results.

I'm very much looking forward to hearing how well your layout works out! If you get closer to the theoretical balancing current values for the circuit, I may have to change my layout and run a new board.

 

[perbear]

John (and others using bq78PL114(S12)),
For the moment I am waiting for the solder paste mask, I did not order it until I was certain the board was bugfree (as far as I can tell from the bare board). But as soon as we know something useful I will post results here or in the Nohassel group.

Per

 

[reagle]

Perbear,
nice disclaimer in silk about catching on fire or exploding! We occasionally make prototypes bright red just to make it very obvious that they may indeed let magic smoke out

 

[CamLight]

LOL, I missed that! Nice feature.

Perbear, getting that solder paste stencil is a good idea. Soldering QFN chips by hand is...umm...interesting.
What was I thinking!?!?!?

Will you be using a small oven or a hot plate to reflow the paste? I'm starting to think I need an oven after the grief I had populating my boards and I'm always interested in hearing others' thoughts. Thanks!

 

[reagle]

I've built my share of boards with QFNs simply by putting a bit of solder on each pad as well as on the device itself, flooding things with flux and using hot air. Most of the time, if you have a very steady hand and stop in time, you can get it to work. The rest of the times you end up with a melted package

 

[CamLight]

That's the way I wanted to do it but didn't have much success. OK, no success at all.

I ended up using paste in a line across the pads for each side and reflowing with hot air (with board at 125C on hot plate). Very, very hard to align the pins though (the paste covers the pads) and the chances for shorting pins is pretty high. But, when I've gotten the alignment right, it's worked really well. Have to check carefully to make sure the chip hasn't slid over one pin from the surface tension if the initial alignment wasn't good.

I need to do another half-dozen boards with a bq78PL114 so I think I'll try your method again. It's just so much easier to set up and I don't need to use paste. This time though with a higher temp presoak on the hot plate to reduce the hot air's job. Perhaps that will get my success rate above 0%.

 

[perbear]

I (or rather my comrades) use a small but professional reflow oven with profile optimized for the leadless solder paste we have been using for several years now. A reflow oven is more or less required since you need to heat the board, parts and past very close to maximum allowable temperature (260°C). Some fine adjustments are usually required since the combination of parts varies quite a lot among the different boards. My board is using TO-252 and possibly TO-263, both soldered power transistor housings similar to TO-220 without bolts.

 

[perbear]

Normally a reflow oven that functions well with QFN and other difficult packages is expensive. You may make one from a toast oven with additional temperature profiling electronics (not expensive). The additional accurate temperature control is important if you use fine pitch components or leadless paste to get optimal reflow.

Here is a link to a complete oven based on an Elektor article (Elektor is a Dutch hobby electronics magazine that is/was also published in German, Swedish and English): https://www.elektor.com/projects/smt-oven.683120.lynkx