ANE (All New Energy) BMS (BMI/LifeBatt/PSI)

[fechter]

Outstanding data. What are you using to graph the cell voltages?

If all the cells were very evenly matched, there would not be so much variation between them.
I'm pretty sure that permanent cell damage occurs around 4.2v.
Between 3.8v and 4.2v, I'm not sure what happens, but I suspect it is still not so good for the cells.
The smaller (Ping) type BMS circuits I've seen do a similar overcharge to around 4.2v on the higher cells.

On my BMS design, no cell will ever exceed the set point (3.67v).

 

[Lanchon]

day 1, one last try...

the charger imposes a total voltage of 57.6V over 16 cells; which is the same thing as saying that it imposes a cell average voltage of 3.6V (57.6V / 16). the VMSes impose a max cell voltage of 3.65V and equal voltages within the 4 bunches. these restrictions mean:

-the 4 bunches have independent voltages
-no bunch can be over 3.65V
-(bunch1 + bunch2 + bunch3 + bunch4) / 4 = 3.6V

assuming 3 bunches are as high as they can be (3.65V) the remaining bunch must be at:

3.6V * 4 - 3.65V * 3 = 3.45V

this means that due to problem B, bunches can be found wandering randomly within the 3.45V ~ 3.65V band.

there are several ways to fix this if I had access to patch the VMS firmware, and not all of them involve communication between the boards. but I don't, so posting about these options here would be a waste of time.

to avoid the problem, I took apart the charger with the hope of increasing its voltage to 58.4V (3.65V * 16). in this ideal case, all bunches would be fixed exactly at 3.65V. (of course tolerances will make this impossible.)

opened it up, found 3 trimmers, educated guessing took me to the right trimmer at the first try. I didn't actually just set it to 58.4V. instead I took the cell average voltage as measured by the VMSes, subtracted it from 3.65V, and multiplied the result by 16 to find out how much voltage THE VMSes THINK the charger is missing. then I measured the current charger voltage and increased it by the calculated amount. very surprisingly, the target for the charger ended up being exactly 58.4V.

trimmed the value and tested just once, and voila...

View attachment 1-5.png

this is the end of day 1, with a fully balanced pack and a smile. when I have some time I'll post about what happened on the following days, if someone's reading. cheers!

 

[Lanchon]

hi there fech!

> What are you using to graph the cell voltages?

LiveGraph working on logs written by my scripts. take a look at this post for details. if you need more info on the physical setup, start reading at the beginning of this thread. the scripts that I posted before are a bit old, I'll post newer versions soon. (the new scripts can control the charging instead of just logging data.)

> If all the cells were very evenly matched, there would not be so much variation between them.

apparently they are very sensitive when fully charged, and a tiny bit of extra charge makes the voltage go through the roof. it's worth noting that the cell that peaks now may not be the same cell that could peak later, if you simply just let the pack rest for a few hours. maybe this is a common thing with LiFePO4?

> I'm pretty sure that permanent cell damage occurs around 4.2v.

the VMS triggers the overvoltage signal (that should cut the charging) at 4.1V, and records an overvoltage event (for warranty purposes) at 4.2V.

> Between 3.8v and 4.2v, I'm not sure what happens, but I suspect it is still not so good for the cells.

I was really surprised that the VMS would be spec'ed to allow anything above 3.65V (it allows up to 4.1V). but a knowledgeable person with PSI told me that the cells can be safely taken to 3.9V without damage, but should not be left there too long.

I personally took an A123 cell well above 5V an left it there for a long time (an hour?). now this cell is part of a xS1P pack and shows absolutely no sign of underperforming compared to the other same-batch nonabused cells. go figure.

> The smaller (Ping) type BMS circuits I've seen do a similar overcharge to around 4.2v on the higher cells. On my BMS design, no cell will ever exceed the set point (3.67v).

well, these BMSes are certainly all DESIGNED this way. of course it's not how I'd do it, but there must be a reason for it, don't you think? beats me!

where's your BMS design described?

 

[GGoodrum]

Yes, I agree with Richard, VERY interesting data, and it confirms what I have always suspected with this VMS concept is that there is a lot of room for improvement in the software mechanization. Your "problem B" issue, as you discovered, is simply because the total charger voltage was not high enough for the shunts to kick in.

"Problem A" is a much bigger issue, in my mind. I am completely surprised the PSI/BMI?VMS guys never did anything about this, as it absolutely will have an effect on cell life. The prototype VMS actually didn't have any shunts. All it had was this charger shutoff function that happened whenever any one of the four cells hit 4.0V. The engineers in Taiwan claimed that the cells were so well matched at the factory, and that their QC ws so tight that the cells didn't need balancing. I tried to argue, along with Bob Mcree, that this just wasn't the case, and that other data seemed to indicate that long-term charging above 3.65V per cell would reduce cell life by a significant amount, but they didn't listen. It wasn't until they did their own testing did they reluctantly agree that some balancing was a good thing, and that they shouldn't charge to 4.0V. The next version of the VMS contained shunts, but only could pass 100 mA of current. Again I took issue with this, but their arguement went back to the QC/matching theory, and that 100mA was more than enough. By this time Bob and I had done enough of our own testing of these cells to know otherwise, but no matter.

In our BMS, Richard added in the clever "throttling" logic to keep any cell in the pack from ever going over the set point (3.67V...). The way it works is that an optocoupled signal is turned on whenever the shunt circuit is fully on. These opto outputs are all ganged together, in a logical "OR" fashion, so that the signal gets turned on if any cell's shunt is fully on. This "ANY SHUNT ACTIVE" signal is then used to control a FET that is connected in series with the negative charger lead. When the signal comes on, the FET turns off, which cuts the charge current off. When this happens, the cell voltage will immediately drop, causing its shunt to turn off. This then turns off the ANY SHUNT ACTIVE signal which then causes the FET to snap back on, restoring the charge current. The shunt then turns back on, once the cell voltage rises, and the cycle repeats. This causes an oscillation that is smoothed out using a cap so that it is at about a 200Hz rate. One thing I had a hard time getting my aching brain around is what happens when multiple shunts are on? It turns out they eventually all get in sync. What also happens is that as the cells become fully charged, the voltage stays up longer before it drops below the 3.67V point, so the the FET ends up being off longer and longer, before coming back on. We have a red-green LED connected to the circuit that is red if the FET is on, and Green if it is off. It stays red all through the CC charge phase and then transistions smoothly to green as the cells become full. We have some "extra" logic that looks for all the shunts to be fully on at the same time, which is an indication that all the cells are about as full as they are going to get, and this "ALL SHUNTS ACTIVE" signal is used to fire an SCR that shuts off the FET for good, until the circuit is reset.

The bottomline is that this throttling capability keeps the cell voltages truly clamped right at 3.67V. The problem with the current VMS implementation is that without some control over the charge current, a shunt circuit will very quickly get swamped, unless the shunt is able to pass the full charge current. As was shown in the above series of tests, a 200mA shunt gets swamped almost immediately, and that was with a 3A charger. Can you imagine what 20A would do?. We use 1/2A to 1A shunt currents, but even this isn't enough without throttling.

What they really need to do is reprogram the OVP signal to simply come on when any of the four shunts are on (i.e. -- cell voltage is at 3.65V...), and then use this signal in the charger to cutoff the current, but only when the signal is active. If the signal goes off, the charge current should be turned back on. What is happening now is that the charger is acting like the signal is like the ALL SHUNTS ACTIVE signal on our BMS, and it shuts off the charger until it is reset.

Anyway, I think this could be a "software only" fix, but getting them to first admit they have a problem, and then agreeing to make a change is going to be quite difficult, I suspect.

-- Gary

 

[Lanchon]

hi Gary,

thanks for the description of your BMS project, very informative.

> Your "problem B" issue, as you discovered, is simply because the total charger voltage was not high enough for the shunts to kick in.

actually, problem B is the extreme sensitivity of the system to charger voltage. there is not a range of accepted values, but only a single exact voltage. and of course since the VMS is not perfect, this voltage will drift over time; I'll post some graphs regarding this.

> In our BMS, Richard added in the clever "throttling" logic to keep any cell in the pack from ever going over the set point

> This causes an oscillation that is smoothed out using a cap so that it is at about a 200Hz rate.

this is a PWM system that regulates the charger current so that it exactly matches the current accepted by the highest cell plus the current drained by its shunt (in average) with the target of keeping the cell voltage constant at 3.67V. if you consider the constant-voltage highest cell as no longer accepting charge, total charging current matches the shunt current of the highest cell.

this is a bit suboptimal. imagine that the charger FET is pulse-width modulating the charge current at 10% duty, making it roughly 10% of its max. during the active phase (10%) of the cycle all shunts are off. this means that the active duty of the shunt of the highest cell is 90%. but a better solution would be to keep it at 100% (no switching); otherwise the charger would be operating at 90% of the max shunt current of the highest cell, instead of at 100% of it, making the balance operation take 11% longer than strictly necessary.

I've implemented a software solution that does this same thing you're doing, but keeps the duty of the highest shunt at 100% instead. it also does a couple other things. I'll post the scripts as time permits.

> One thing I had a hard time getting my aching brain around is what happens when multiple shunts are on?

as said, PWM charging will match the charge current to the current of the highest cell plus its shunt (which will operate at a high duty cycle). the other cells will of course receive the same current, but their shunts will feature a lower duty cycle (maybe zero), so the cells will climb. but their PWM active phase will be completely shadowed (will "fit inside") the active phase of the highest cell, so they are immaterial to the charge current regulation and can be disregarded.

> We have some "extra" logic that looks for all the shunts to be fully on at the same time, which is an indication that all the cells are about as full as they are going to get

this is of course not exactly true for various reasons, but I guess that when doing things the analog way it's a good tradeof for simplicity. my current software does a more complex thing but it's probably not quite right yet (haven't tested).

 

[Lanchon]

ok, day 2...

next day and without having used the pack I charged it again:

View attachment 2-1.png

we can see two things:

-after perfectly balancing the pack and only 24hs of storage, imbalance is enough to raise the voltage of a cell up to 4.0V. clearly this problem A is serious. I don't have a clue why they chose to admit up to 4.1V voltage before triggering the protection.

-because of drift (either of the charger voltage or of the sensing VMS boards or both) the charger is now 40mV * 4 below the target. problem B was not solved by careful trimming because the system has zero tolerance for drift.

so I trimmed the charger again, but instead of bringing it exactly on target, this time I placed it slight above it. this is how it looked like:

View attachment 2-2.png

since the charger is a 3A CCCV, it will source up to 3A to bring the voltage up to it's own target. on the other hand, the VMSes will shunt up to 200mA to lower the voltage to their combined target. there's no question about what will happen: the shunts will operate to maximum capacity and the charger will source enough current to override them and charge the cells too, and will succeed at imposing it's own voltage target.

after reaching equilibrium, the total current will match the current of the least capable shunt. also, all cells will be at or above 3.65V, because if not their shunt would turn off and the cells would charge approximately at 200mA till they reach the threshold. all shunts will be nearly at 100% duty (those cells above 3.65V will be exactly at 100% duty) meaning that bunch control is lost; the individual cells will drift on their own. also, the VMS chain will dissipate its combined absolute maximum power and will remain in this state until the charging is manually stopped. the total voltage imposed by the charger will keep some cells overvolted. really ugly situation...

the VMSes did get hot, and at about minute 14 into the charge I retrimmed the charger live. I placed it just a tiny bit below the target, and left it there up to this day.

to recap on problem B:

1) if the charger voltage is below the VMS chain target:
. a) cell bunches will drift below 3.65V, according to the total voltage constraint.
. b) shunts will be near 0% duty and will only be used to clamp the bunches together.
. c) the charger can potentially detect end of charge.

2) if the charger voltage is above the VMS chain target:
. a) individual cells will drift above 3.65V, according to the total voltage constraint.
. b) for the same charger to VMS voltage difference, individual cells can potentially depart form the 3.65V ideal BY 4 TIMES AS MUCH VOLTAGE compared to case 1); the reason is that in this case cells are allowed to drift on their own instead of in bunches. (but note that resistive shunts will increase their current with increasing cell voltage, so cells will slowly tend to a stable configuration where they'll want to stay. this does not mean they'll be balanced, because the equilibrium state depends on many factors, but rather that it may be improbable that a single cell shoots up too much compared to the others.)
. c) shunts will be near 100% duty and the VMS chain will dissipate its maximum power.
. d) the charger will never see the current go below the shunt current.

3) the charger voltage and/or the VMS voltage sensing will drift around, and (theoretically) it won't be possible to match them.

this holds true for an ideal CCCV charger, but things are better for a real one.

the problem with an ideal CCCV charger is that it will source its maximum current for any voltage below its target, no matter how close to target it is. if the charger has some internal series resistance, or external series resistance is present (in the form of cabling or a fuse for instance), then things change. call this series resistance R. when the load is slowly raising in voltage and causes the transition from CC to CV, the charger will reach target before the load does (due to the voltage drop in R) and current will begin to tapper down from this point onwards. as the load nears the voltage target, the voltage across R will go down, and thus so will the charge current.

this means that when R is introduced, the CC-CV transition will "soften" and the charge current will progressively diminish from max to zero across a voltage range of the load that exists right below the target voltage.

this means that one way to solve problem B is to raise the charger voltage target and introduce a series resistor so that the charge current when all the cells reach the "shunts fully on" target voltage is guaranteed to be in a range manageable by the shunts, no matter how much the relevant voltages are drifting.

VC: charger voltage target (with its tolerance VCtol)
VP: pack (VMS chain) voltage target (with its tolerance)
R: series resistance of the circuit
i: trickle charge current (current when pack is fully charged) (with its tolerance)

i = (VC - VP) / R, so:

imax = (VCmax - VPmin) / R
imin = (VCmin - VPmax) / R
VCmax - VCmin = 2 * VCtol

now say you want a trickle imax of 100mA because you don't want to stress the VMS with too much power dissipation. and say you want an imin of 50mA to compensate for self-discharge and to cover the VMS chain power budget.

now solve the 3 eqs above for VCmax, VCmin and R (the other vars are given), and problem B is history! (make sure you choose an R that can handle the power dissipation imposed by the max charge current of the charger.)

now, some series resistance seems to exist in my setup, because since the last charger trim many days passed and the system has for now always behaved correctly. this is typical:

View attachment 3-1.png

problem A remains. in this case I used an external shunt over the blue cells. I turned off the charger when this shunt started to sink them below 3.65V, because the rest of the cells would be forced above this level (due to the constant total voltage principle). you can see them starting the climb just before the interruption. on the next charge the blue cells lag below, but after resting a bit the third charge shows that they want to lead again.

back to problem B. with the last charger trim, sometimes the cells are just perfect and sometimes a few cells lag below just a tiny bit. you can see this in the red bunch near the middle of the graph. this is as low as I have seen them go for now. it seems that I'm lucky: the series resistance of the system seems JUST ENOUGH to accommodate the voltage tolerances, and so I haven't had the need to add series resistance. but this is extremely dependent on setup, and you may not get this lucky. maybe if I burn the charger output fuse, the next one won't play as nice.

speaking of which, an easy way to add some resistance might be to find a suitable output fuse. different sizes and technologies might give you some range to choose from.

I have the pending assignment of at least measuring the current in this state a couple of times. I guess it is low because sometimes the cells lag, and also because the VMS chain never gets hot. but the resistance of the measurement instrument may completely cloud the results since during the CV phase the circuit is all very low impedance. (think battery and voltage source!)

 

[Lanchon]

hi Gary, fech,

one more comment on your BMS. (I know it only by what you posted on this thread.)

when the charge FET is off, the charger climbs to its max voltage and stays there. when the FET turns on, basically it shorts the charger to the battery, which has very low impedance. if the charger has capacitors across its output stage, a very big current surge could arise while the caps discharge to the voltage level of the pack. this spike can exceed the instantaneous max current of several components, including the FET and the caps on the charger and could make them fail.

with the FET running at 200Hz the additional problem of power dissipation comes to mind, particularly regarding the caps. these may be cheap alu caps with a relatively high ESR and could easily heat up with the repeated current spikes. the heated caps probably won't last long.

I see no reason to operate the FET at such a high frequency but maybe I'm missing something. I don't know how your circuit is designed, but maybe you can force a minimum off time for the FET, say in the order of a second. after that the cells will take more time than before to reach the threshold again, but the duty cycle will be maintained. (frequency in this case would not be constant.) you could also choose to up the threshold a bit to compensate the fact that the mean voltage will be a bit below the threshold.

my implementation is a bit different (it looks like a 1-bit delta sigma modulator running at a constant sample rate of 0.2Hz) and at any given time it won't switch at a particular frequency; the switching looks more like noise. however the fastest switching frequency allowed is 0.1Hz, 3 orders of magnitude below your implementation.

maybe you could consider lowering the frequency to avoid power dissipation issues; some chargers may do fine while others might suffer, so it may pay to lean towards the safer side.

one more thing; when the FET turns off, inductance on the charger and charger wire might expose the FET to a high voltage and might progressively damage it or make it fail on the spot. ANE's cutoff board does NOT protect the charge FET in any way. (it does protect the discharge FET, though; it's simpler to do that.)

an obvious way to protect the FET is by having a cap across the charger input of the BMS... but this exacerbates the problem I mentioned before! someone trained in switching supplies would probably think about adding an inductance and a diode on the other side of the FET, but since here we can lower the frequency so much, a simple snubber circuit across the FET could do the trick. it would dissipate some energy per FET toggle, but at low frequencies the mean power would be very low.

 

[rkosiorek]

lanchon,

one of my questions concerns the math for the selection of the series resistor. specificaly the term VCtol. that would be the tolerance of the of the output from the charger. usually specified as +/- (X) Volts. My theoretical charger outputs 58.4V +/- 0.2V. the voltage could swing from 58.2V to 58.6V. do i use 0.4V as the VCtol?

rick

 

[miro13car]

I charge my 36V10Ah HPS with 10A Soneil.
When I first start using Soneil I was making mistake of disconnecting charger right after end of charge LED went on.
I was getting 3 long beeps so I decide to keep charger on longer for hour or 2 .
Result : cells balanced to within 0.05V differences.
MC

 

[rkosiorek]

this schematic is incorrect. do not use it

After reading lanchon's critique of my first breakout board i have revised the schematic per his suggestions. some of the changes that were made:

View attachment 1

1. adding 2 opto's to fully isolate the RS232 signals to the USB to TTL converter. the power of these opto's is supplied by the PC-USB connector on one side so the PC and USB is isolated from the VMS/Battery pack.

2. Reconfigure the "Wake" switch so that it switches VMS +5V through a 10K resistor to the VMS "Wake" pin.

3. adding a jumper so that the GND and GND_L can be shorted together if desired. this may be desired if the "Display Board" is connected to the Lowest VMS in the system. by that i mean the VMS board that is connected to the B(-) output of the pack. otherwise i think it should be left open.

4. some testing has shown that the OVP, LVP and BUZZ signals cannot source as much current as the Tx and Rx lines. the values of the opto isolators were adjusted to provide higher gain.

i have collected the parts to breadboard this circuit and i will give it a try in the next couple of days.

i also downloaded the TCL/TK package for windows as well as lanchon's earlier scripts. after i get the breakout board connected the next challenge will be to get the software running on my Vista Laptop i guess.

rick

 

[Ypedal]

Rick, do you already have , or would you like the boards to play with ? :wink:

 

[fechter]

hi Gary, fech,

one more comment on your BMS. (I know it only by what you posted on this thread.)

when the charge FET is off, the charger climbs to its max voltage and stays there. when the FET turns on, basically it shorts the charger to the battery, which has very low impedance. if the charger has capacitors across its output stage, a very big current surge could arise while the caps discharge to the voltage level of the pack. this spike can exceed the instantaneous max current of several components, including the FET and the caps on the charger and could make them fail.

with the FET running at 200Hz the additional problem of power dissipation comes to mind, particularly regarding the caps. these may be cheap alu caps with a relatively high ESR and could easily heat up with the repeated current spikes. the heated caps probably won't last long.

The -really- long winded discussion of it is here: http://endless-sphere.com/forums/viewtopic.php?f=14&t=5416

Yes, the throttling circuit is crude, but the cells don't really act like capacitors as much as you might think. There are quite a few of these out there and cap and FET heating does not seem to be an issue at charge currents up to 20A. The peak current when the switch turns on is not excessive as long as the voltage differential is reasonable. There is always some resistance in the charger wires to help limit it. The voltage difference between the unloaded charger and the pack during throttling is usually only a few volts. We use a FET that has some overkill in the current department anyway.

The other implementation of my circuit is to use the feedback from the cell optocouplers to control the PWM inside the charger directly. This eliminates all the nasty switching outside and maintains the maximum possible charge current. This is recommended for larger packs.

In the latest revision of the externally throttled circuit, I reduced the PWM frequency from 20khz to 200hz. It could easily be made slower, but I suspect there won't be much advantage to it. Also keep in mind that throttling does not usually start until the bulk charge has mostly finished and the charge current is starting to taper.

Protecting against inductive spikes was considered, but as you point out, placing a capacitor across the the input is not really good. It might work to use a transorb or similar device. Our approach has simply to use a FET with a higher than needed voltage rating. There is typically not much inductance in the wiring and the charger has a capacitor across its output.

 

[rkosiorek]

Rick, do you already have , or would you like the boards to play with ? :wink:

Gaston,

i have 4 of the boards so far. but that is short of the number of boards that i need.

are you looking to trade some of your boards?

rick

 

[Lanchon]

lanchon,

My theoretical charger outputs 58.4V +/- 0.2V. the voltage could swing from 58.2V to 58.6V. do i use 0.4V as the VCtol?

rick

no, use 0.2V. this equation makes that clear:

> VCmax - VCmin = 2 * VCtol

 

[Lanchon]

I charge my 36V10Ah HPS with 10A Soneil.
When I first start using Soneil I was making mistake of disconnecting charger right after end of charge LED went on.
I was getting 3 long beeps so I decide to keep charger on longer for hour or 2 .
Result : cells balanced to within 0.05V differences.
MC

that's something I wanted to discuss. the VMS beeps 3 times when a cell reaches 3.9V. at 4.1V it disconnects the charger, and when cells relax below 3.5V it connects the charger again. a CCCV charger would then overvolt the cell again and again.

but some chargers detect end of charge (current low condition, zero in this case) and go into trickle charge mode. trickle is effectively CCCV again but the current limit is much lower (voltage might also be different). if trickle current is less than shunt current and voltage is high enough, cells will balance.

 

[Lanchon]

rk,

> 1. adding 2 opto's to fully isolate the RS232 signals to the USB to TTL converter. the power of these opto's is supplied by the PC-USB connector on one side so the PC and USB is isolated from the VMS/Battery pack.

> 2. Reconfigure the "Wake" switch so that it switches VMS +5V through a 10K resistor to the VMS "Wake" pin.

> 3. adding a jumper so that the GND and GND_L can be shorted together if desired. this may be desired if the "Display Board" is connected to the Lowest VMS in the system. by that i mean the VMS board that is connected to the B(-) output of the pack. otherwise i think it should be left open.

the docs that I have are not clear on which ground is which on the DB9. one, call it input ground or ignd or car ground (as it is called on some ANE docs), is floating and NOT connected to the pack's ground. the other one, call it output ground or ognd or VMS ground (as it is called by ANE), is. so you can figure out which is which by testing conductivity the the pack's ground.

the ignd is the negative return of the input optos that are present on the VMS board. but the +5V output is relative to ognd, so connecting the +5V pin to either input won't do a thing! you must also connect the two grounds together so that current can flow though the input optos.

this means that your circuit won't work without the jumper installed. and removing the jumper does not really isolate the grounds, as ignd remains connected via the optos and the +5V regulator to ognd.

so you have two options:

1) fully float the grounds: a) keep ognd and ignd separate. b) make sure all VMS outputs, after going through their opto, return only to the ognd pin. c) remove the wakeup button (it can't work without an external power source). d) tie ignd to USB bridge ground. e) remove the opto linking the USB bridge TX output to the VMS RX input and link it directly (the VMS already has optos on inputs).

note: a wakeup button could be operated using the USB +5V signal, but you'd need a USB host to do that; pretty worthless...

2) tie the grounds together: a) remove the jumper and tie the grounds for good. b) the opto linking the USB bridge TX output to the VMS RX input is now needed, but the way you've drawn it it will invert the signal. maybe you need the signal to go through without inversion; in this case you can tie the VMS RX input to +5V inserting in series a current limit resistor an your opto's output transistor.

notes applicable to 1) and 2):

-I haven't checked the polarity of any of the signals. (I don't think there's enough info on ANE's docs, but maybe I'm wrong and there is.)

-in both circuits you can make the USB bridge TX output drive both the VMS RX input and the wakeup input. this is the way ANE does it, and the way I use it, and my scripts support this (will wake before sending commands).

> i also downloaded the TCL/TK package for windows as well as lanchon's earlier scripts.

I'll post the newer ones when I have some time to sort them out.

 

[rkosiorek]

well i guess i'll have to do some checking on the circuit. back to the drawing board.

on the other hand I now have a 24V pack to use it with. i havent finished the cases yet but this is a look at the 24V 10Ah pack. the VMS boards are mounted behind a clear lexan cover.

 

[Lanchon]

that's a very handsome pack!

I can't see the ribbon-cable-to-DB9 board, whatever it's name is. don't you have one? do you have the pinout of the ribbon connector?

 

[rkosiorek]

yep it's in there. it is right next to the cells bellow the VMS boards.

rick

 

[Lanchon]

fech, oh man, I didn't know there was an 87 page discussion! I guess every possible idea must have been tossed around a couple of times, but just in case:

> cap and FET heating does not seem to be an issue at charge currents up to 20A

good to hear that, sometimes I tend to "overdesign" a bit. anyway, for larger devices you could do this in order: charger, optional series inductor to filter high di/dt on the charger wires, cap across to protect fet, fet, diode across to route current from next inductor back to charge the pack, inductor in series to limit inrush current when fet turns on, pack. (the current on the inductors can safely drop to zero, so they don't need to be big.)

>Protecting against inductive spikes was considered, but as you point out, placing a capacitor across the the input is not really good.

or if the inrush current is tolerable you could protect the fet with a resistor and capacitor in series from fet source to drain. the snubber will waste energy on each fet switch but at low frequencies it'd be negligible.

 

[Lanchon]

Ypedal,

sorry I forgot! so there are two problems with these VMS boards. problem B, cells not ending up being balanced, was discussed earlier. problem A, cells overvolting, can be dealt with in several ways:

-analog: if charge current is limited to < 200mA cells won't overvolt. you could add a resistor in series so that when total pack voltage approaches the charged state the current is small. of course this resistor must tolerate the full amperage of the charger. a lightbulb comes to mind. if you have a 3A charger, a 6V 18W lamp will drop 6V at full charge current. this means that the charger will enter the CV phase and begin throttling when the pack is at 6V less than the charger's target voltage. this will slow the later stages of charge but will make the thing work.

you could use different lamps for different pack states. you could use one of higher resistance to charge the pack after long storage when the cells are expected to be widely unbalanced and a lower resistance lamp for everyday charging.

-digital control: or if you have a FET or relay that can cut the charger off when the OVP signal is triggered (the way this VMS is supposed to be used) you could do this:

-some chargers detect end of charge and switch to a small trickle current. if you have such a charger and the trickle current is less than 200mA you can just let the system be: the VMS will cut the charger when one cell reaches 4.1V and the charger will then switch to trickle. when all cells drop below 3.5V the VMS will reconnect the charger and the trickle will top and balance all cells.

-4.1V seems way too high, I can't understand why they picked such a high value. there a couple of VMS commands to force the OVP and LVP signals. if you are willing to let a laptop beside the pack while charging, the laptop can monitor the cells and disconnect the charger momentarily at any voltage you choose. this will switch the charger to trickle and cells won't overvolt.

-if your charger doesn't do trickle, you can use a script that connects and disconnects the charger in order to keep the cells around say 3.7V during balancing, much like fechter's solution.

I've got a script for these things.

 

[Lanchon]

I had access to an ANE USB/cutoff board (the one shown in these pictures) but not to a VMS board. I had no docs, not even a USB cable for the board, I didn't know it had USB at all. I had to rev eng this cutoff board to find out how to use the 10-pin flat cable connector used to bind all the VMS boards, the protocol, etc. some people are trying to make charge and discharge switches for the VMS. I'll post my findings to help them. this info is for educational purposes only, these circuits could be protected by IP laws.

EDIT: please excuse the use of the portable schematic capture device...

View attachment 7

View attachment 2 - Power Section.jpg

View attachment 3 - Charge Gate Driver.jpg

View attachment 4

View attachment 5 - Buzzer.jpg

View attachment 6 - USB To Serial Birdge - USB Side.jpg

View attachment 1

View attachment 8 - Parts.jpg

 

[AndyH]

Lanchon,

Fantastic job reverse engineering the boards! Your portable CAD/schematic capture solution is much neater than mine!

I know that I've sent you and rkosiorek documents, but don't recall if they included the docs for the active cut boards. So...just in case... I now have docs and software drivers for both USB/cut-off boards - the 30A and 60A continuous solutions. I also have the docs for both variants of the VMS boards, the data interface / communications data docs, and the software for monitoring data from the VMS/USB board combination.

Let me know if you want them for your collection.

I've got an 8S battery assembled for comparing the VMS and Goodrum/Fechter BMS side by side. Four cells on a VMS and four on a BMS. All eight are monitored with a PakTrakr for data collection. I'll start cycling the pack once my 24V chargers arrive. It's likely to be a slow process, though, because I've been swamped with BMS building.

Andy

 

[rkosiorek]

Lanchon,

Fantastic job reverse engineering the boards! Your portable CAD/schematic capture solution is much neater than mine!

I know that I've sent you and rkosiorek documents, but don't recall if they included the docs for the active cut boards. So...just in case... I now have docs and software drivers for both USB/cut-off boards - the 30A and 60A continuous solutions. I also have the docs for both variants of the VMS boards, the data interface / communications data docs, and the software for monitoring data from the VMS/USB board combination.

Let me know if you want them for your collection.

I've got an 8S battery assembled for comparing the VMS and Goodrum/Fechter BMS side by side. Four cells on a VMS and four on a BMS. All eight are monitored with a PakTrakr for data collection. I'll start cycling the pack once my 24V chargers arrive. It's likely to be a slow process, though, because I've been swamped with BMS building.

Andy

please and thank you andy. i'm very much interested in any and all information i can get.

i could use more information.

rick

 

[Lanchon]

hi Andy,

same here, please do send everything you think might help, and thank you very much again!