I find that it's much easier to think about the questions of capacitors, ESR, ESL, etc from a frequency-domain perspective.
If you dig all the way down, the goal is for the FETs to see an ideal voltage source with zero or very low impedance at all frequencies present in the current waveform. The last part is the key.
Let's think about what the frequency content of the current is going to look like. Obviously there is a large DC component. There will be large components at the PWM frequency and it's harmonics. Pat is also absolutely correct that the switching transients contain a lot of higher-frequency energy. If the turn-on/off times are 1 us, that will add components at 1 MHz and higher harmonics. That means that we need to make sure the FETs see a low impedance from DC to around 10 MHz or so.
We all know that the battery is not an ideal voltage source. The battery and wires have resistance and inductance. The resistance is pretty small with good batteries, but the inductance is a problem because it means the battery has high impedance at high frequencies (Z = j*w*L, where w=2*pi*f). That's where the capacitors come in, because an ideal cap has zero impedance at high frequencies.
Of course, capacitors aren't ideal either. They have some series resistance which we call ESR, and some series inductance we call ESL. The effect of this is that, if you look at a plot of impedance vs. frequency for a real capacitor, it will look like a "V". The point of the "V" is called the resonant frequency, which is where the ESL exactly cancels out the cap's reactive impedance (Z=1/j*w*C), leaving only the ESR. Above that frequency, the impedance rises because the ESL is now dominant. Bottom line: ESR determines what the minimum impedance of the capacitor will be, and the resonant frequency tells you how high the frequency can get before it becomes useless.
The big can electrolytics usually have resonant frequencies in the 10-100 kHz range. Good quality, low-ESR versions are usually 50-100 kHz, which is what we'd be using. This should be a clue that you need something more than just the electrolytics to deal with those high-frequency transients. Tantalum caps are a good option, but they can be pricey and often don't have high enough voltage ratings, so ceramic capacitors are the best option. MLCC chip capacitors are very good for this. Their resonant frequency is determined mostly by the package size and the dielectric type (the better dielectrics like C0G have better frequency characteristics, but the higher-value caps we need are usually X7R). A medium-sized package like 0805 usually has a resonant frequency around 10 MHz. Smaller packages have higher frequencies, larger packages have lower frequencies.
What a good design should do is choose 3 or 4 different cap values and packages, with resonant frequencies spread across the desired range, and use any many of each as you need to get the desired ESR value. The combined impedance will give us what we want, which is a uniformly low impedance across a wide range of frequencies.
The above is a LOT more important than just the bulk value of the capacitor (as many others have said already). We do need a certain amount of capacitance to supply current, but it's probably smaller than you think. It turns out that 1000 uF is enough to supply 100A for a full 20 kHz PWM period (50 us) with only 5V of sag. That's the capacitor supplying the entire current as if the battery weren't even there. Realistically, the caps only need to supply lots of current for a few us, and that doesn't require a huge amount of capacitance. That 1000 uF cap can supply 100A for 2 us with 0.2V sag. But it would require 2 milliohm ESR to achieve the same sag, which is obviously the stricter spec. But, the bulk of the current during these very quick transients will actually be coming from the smaller ceramic caps, so their (much lower) ESR is as or more important in reducing the transient ripple than the ESR of the big caps.
I also wanted to point out that Alan's math about the ESR-related heating is not quite right. The cap will not be supplying 50A on a continuous basis, so we need to calculate the RMS current to find the power dissipation. Since the cap is generally only supplying short pulses of current at a small duty cycle, the RMS current will be a small fraction of the peak current, maybe 2-5%. The power dissipation is then 1/2*Irms^2*ESR, which would be something like 30 mW assuming a 2.5 Arms current. Most of the big electrolytics are rated for 500-1000 mA each, which takes into account the ESR-related heating.
Gary would have been though a half dozen iterations of the circuit board by now :lol:
It seems that it doesn't really take such a big driver chip to quickly switch 400~500nC or so of FETs (2X IRFB3006's). Using TI's UCC27201 driver rated at 3A peak I get switching times quite a bit under 500ns on+off combined under full load (from memory - I am setting up new diffferent FETs right now for new tests). This is using 10ohm gate drive resistors, so with bigger FETs the resistors could be lowered to try and maintain good switching times. I don't think we really need insanely huge gate drive chips for ebike sized applications, even for the more extreme ones.
