The bus bars still appear to be in the way of the FETs. If you made them wider, they could be thinner (8x2mm copper) and still have less resistance than 6 AWG copper. That way you could place the bus bars under the FETs.
I see significant areas where VDC and GND are next to each other on the same layer - I'd still throw some ceramics in there. 2x100v in series, and as many as will fit in parallel. Cheap and if they aren't needed you can leave some or all of them out in the final version.
Your gate drive traces are still running under a current-carrying trace, but less so. From my experience, inductive turn-on might be an issue. I would use pairs of traces, right on top of one another, running to the gate and source pins. Have the VDD pin of the gate driver connected to the source pin, not directly to ground. Put the capacitor between VDD and GND and place a low-value resistor (2-4 ohm) in between your gate drive supply and VDD. Something like this:
View attachment 288105
I'm using twisted pairs for this (total and utter PITA) but you could achieve the same result with traces on adjacent layers.
Other than that it's looking really nice. If you select shorter electrolytic capacitors this controller would be pretty small for the watts it puts out. I'm thinking about putting the FETs horizontally (rather than vertically) on my next design as well. Would save a lot of space.