Can you describe the issue in details? Do you think it's the power PCB layout or coupling between the stacked boards?
I made a few similar boards for testing in the past few years and I know there are issues with the stacked structure but those are mostly manageable, although basically better to prevent them by placing the low voltage circuits far from the switching power circuits.
In my case I could identify 2 main issues:
One is that the multiple GND connections from the controller board to the power FET sources (3 connectors for 3 low side FETs) generate voltage on the controller board GND plane, because the FET sources are not on the same potential during the switching transients. This GND noise can even be rectified on the pin protection diodes of the ICs and raise the supply voltage from 3.3V to e.g. 3.6V or more. It can be fixed with low impedance GND plane on the controller board and adding small serial resistors to the source connectors, i.e. a part of the gate resistor is placed in the source line.
The other one is that the high current switching induces voltage in wire loops on the controller board. The solution was also a low impedance GND plane for shielding on the side of the controller board that faces the power board, and making sure there are only short signal wires (or no wires at all) on this plane and no large loops.